Cd16d
60a8aa912d
- Created a new Block Design Archive (lab_3.bda) for LAB3, defining nodes and edges for the design. - Added a placeholder README file in the simulation directory. - Initialized a Vivado project file (lab3.xpr) with configuration settings and source files for synthesis and simulation. - Updated vhdl_ls.toml to include LAB3 source and simulation files for VHDL language server support.
14 lines
720 B
Tcl
14 lines
720 B
Tcl
# SPI connected to JA, top row
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set_property PACKAGE_PIN J1 [get_ports SPI_M_0_ss_io]
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set_property PACKAGE_PIN G2 [get_ports SPI_M_0_sck_io]
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set_property PACKAGE_PIN L2 [get_ports SPI_M_0_io0_io]
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set_property PACKAGE_PIN J2 [get_ports SPI_M_0_io1_io]
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set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io0_io]
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set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io1_io]
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set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_sck_io]
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set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_ss_io]
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set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io0_io]
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set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io1_io]
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set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_sck_io]
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set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_ss_io]
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