160 lines
6.0 KiB
Verilog
160 lines
6.0 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Digilent & Politecnico di Milano
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// Engineer: Arthur Brown, Nicola Corna, Fabio Garzetti, Nicola Lusardi
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//
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// Create Date: 14/05/2019
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// Module Name: axis_i2s
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// Description: AXI-Stream I2S controller
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// Generates clocks and select signals required to place each of the ICs on the Pmod I2S2 into slave mode.
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// Data is 24-bit, shifted one serial clock right from the LRCK boundaries.
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// This module only supports 44.1KHz sample rate, and expects the frequency of axis_clk to be approx 22.591MHz.
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// At the end of each I2S frame, a 2-word packet is made available on the AXIS master interface. Further packets will be discarded
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// until the current packet is accepted by an AXIS slave.
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// Whenever a 2-word packet is received on the AXIS slave interface, it is transmitted over the I2S interface on the next frame.
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// Each packet consists of two 3-byte words, starting with left audio channel data, followed by right channel data.
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//
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.02 - Use 24-bit interfaces
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module axis_dual_i2s (
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input wire axis_clk, // require: approx 22.591MHz
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input wire axis_resetn,
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input wire [23:0] tx_axis_s_data,
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input wire tx_axis_s_valid,
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output reg tx_axis_s_ready = 1'b0,
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input wire tx_axis_s_last,
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output wire [23:0] rx_axis_m_data,
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output reg rx_axis_m_valid = 1'b0,
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input wire rx_axis_m_ready,
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output reg rx_axis_m_last = 1'b0,
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output wire tx_mclk,
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output wire tx_lrck,
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output wire tx_sclk,
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output reg tx_sdout,
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output wire rx_mclk,
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output wire rx_lrck,
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output wire rx_sclk,
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input wire rx_sdin
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);
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reg [8:0] count = 9'd0;
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localparam EOF_COUNT = 9'd455; // end of full I2S frame
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always@(posedge axis_clk)
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count <= count + 1;
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wire lrck = count[8];
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wire sclk = count[2];
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wire mclk = axis_clk;
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assign tx_lrck = lrck;
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assign tx_sclk = sclk;
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assign tx_mclk = mclk;
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assign rx_lrck = lrck;
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assign rx_sclk = sclk;
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assign rx_mclk = mclk;
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/* AXIS SLAVE CONTROLLER */
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reg [23:0] tx_data_l = 0;
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reg [23:0] tx_data_r = 0;
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always@(posedge axis_clk)
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if (axis_resetn == 1'b0)
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tx_axis_s_ready <= 1'b0;
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else if (tx_axis_s_ready == 1'b1 && tx_axis_s_valid == 1'b1 && tx_axis_s_last == 1'b1) // end of packet, cannot accept data until current one has been transmitted
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tx_axis_s_ready <= 1'b0;
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else if (count == 9'b0) // beginning of I2S frame, in order to avoid tearing, cannot accept data until frame complete
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tx_axis_s_ready <= 1'b0;
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else if (count == EOF_COUNT) // end of I2S frame, can accept data
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tx_axis_s_ready <= 1'b1;
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always@(posedge axis_clk)
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if (axis_resetn == 1'b0) begin
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tx_data_r <= 24'b0;
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tx_data_l <= 24'b0;
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end else if (tx_axis_s_valid == 1'b1 && tx_axis_s_ready == 1'b1)
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if (tx_axis_s_last == 1'b1)
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tx_data_r <= tx_axis_s_data;
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else
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tx_data_l <= tx_axis_s_data;
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/* I2S TRANSMIT SHIFT REGISTERS */
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reg [23:0] tx_data_l_shift = 24'b0;
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reg [23:0] tx_data_r_shift = 24'b0;
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always@(posedge axis_clk)
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if (count == 3'b000000111) begin
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tx_data_l_shift <= tx_data_l[23:0];
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tx_data_r_shift <= tx_data_r[23:0];
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end else if (count[2:0] == 3'b111 && count[7:3] >= 5'd1 && count[7:3] <= 5'd24) begin
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if (count[8] == 1'b1)
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tx_data_r_shift <= {tx_data_r_shift[22:0], 1'b0};
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else
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tx_data_l_shift <= {tx_data_l_shift[22:0], 1'b0};
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end
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always@(count, tx_data_l_shift, tx_data_r_shift)
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if (count[7:3] <= 5'd24 && count[7:3] >= 4'd1)
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if (count[8] == 1'b1)
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tx_sdout = tx_data_r_shift[23];
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else
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tx_sdout = tx_data_l_shift[23];
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else
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tx_sdout = 1'b0;
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/* SYNCHRONIZE DATA IN TO AXIS CLOCK DOMAIN */
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reg [2:0] din_sync_shift = 3'd0;
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wire din_sync = din_sync_shift[2];
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always@(posedge axis_clk)
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din_sync_shift <= {din_sync_shift[1:0], rx_sdin};
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/* I2S RECEIVE SHIFT REGISTERS */
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reg [23:0] rx_data_l_shift = 24'b0;
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reg [23:0] rx_data_r_shift = 24'b0;
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always@(posedge axis_clk)
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if (count[2:0] == 3'b011 && count[7:3] <= 5'd24 && count[7:3] >= 5'd1)
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if (lrck == 1'b1)
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rx_data_r_shift <= {rx_data_r_shift, din_sync};
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else
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rx_data_l_shift <= {rx_data_l_shift, din_sync};
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/* AXIS MASTER CONTROLLER */
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reg [23:0] rx_data_l = 24'b0;
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reg [23:0] rx_data_r = 24'b0;
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always@(posedge axis_clk)
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if (axis_resetn == 1'b0) begin
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rx_data_l <= 24'b0;
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rx_data_r <= 24'b0;
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end else if (count == EOF_COUNT && rx_axis_m_valid == 1'b0) begin
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rx_data_l <= {8'b0, rx_data_l_shift};
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rx_data_r <= {8'b0, rx_data_r_shift};
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end
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assign rx_axis_m_data = (rx_axis_m_last == 1'b1) ? rx_data_r : rx_data_l;
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always@(posedge axis_clk)
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if (axis_resetn == 1'b0)
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rx_axis_m_valid <= 1'b0;
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else if (count == EOF_COUNT && rx_axis_m_valid == 1'b0)
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rx_axis_m_valid <= 1'b1;
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else if (rx_axis_m_valid == 1'b1 && rx_axis_m_ready == 1'b1 && rx_axis_m_last == 1'b1)
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rx_axis_m_valid <= 1'b0;
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always@(posedge axis_clk)
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if (axis_resetn == 1'b0)
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rx_axis_m_last <= 1'b0;
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else if (count == EOF_COUNT && rx_axis_m_valid == 1'b0)
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rx_axis_m_last <= 1'b0;
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else if (rx_axis_m_valid == 1'b1 && rx_axis_m_ready == 1'b1)
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rx_axis_m_last <= ~rx_axis_m_last;
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endmodule
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