Cd16d
b11c65043f
- Created board.xit for physical constraints related to UART interface. - Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata. - Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl. - Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings. - Configured file sets and simulation options for both projects.
18 lines
590 B
Plaintext
18 lines
590 B
Plaintext
package require xilinx::board 1.0
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namespace import ::xilinx::board::*
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set instname [current_inst]
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set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc]
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puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n"
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if { [get_project_property BOARD] == "" } {
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close_ipfile $f_xdc
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return
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}
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set board_if [get_property PARAM_VALUE.UART_BOARD_INTERFACE]
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if { $board_if ne "Custom"} {
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board_add_port_constraints $f_xdc $board_if TxD UART_TX
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board_add_port_constraints $f_xdc $board_if RxD UART_RX
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}
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close_ipfile $f_xdc
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