Cd16d
b11c65043f
- Created board.xit for physical constraints related to UART interface. - Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata. - Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl. - Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings. - Configured file sets and simulation options for both projects.
288 lines
7.1 KiB
Plaintext
288 lines
7.1 KiB
Plaintext
{
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"design": {
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"design_info": {
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"boundary_crc": "0x82F7CD001DE2BC1E",
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"device": "xc7a35tcpg236-1",
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"name": "loopback_I2S",
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"rev_ctrl_bd_flag": "RevCtrlBdOff",
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"synth_flow_mode": "None",
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"tool_version": "2020.2",
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"validated": "true"
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},
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"design_tree": {
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"proc_sys_reset_0": "",
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"clk_wiz_0": "",
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"proc_sys_reset_1": "",
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"axis_dual_i2s_0": "",
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"system_ila_0": ""
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},
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"ports": {
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"reset": {
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"type": "rst",
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"direction": "I",
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"parameters": {
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"INSERT_VIP": {
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"value": "0",
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"value_src": "default"
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},
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"POLARITY": {
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"value": "ACTIVE_HIGH"
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}
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}
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},
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"sys_clock": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"CLK_DOMAIN": {
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"value": "loopback_I2S_sys_clock",
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"value_src": "default"
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},
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"FREQ_HZ": {
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"value": "100000000"
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},
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"FREQ_TOLERANCE_HZ": {
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"value": "0",
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"value_src": "default"
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},
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"INSERT_VIP": {
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"value": "0",
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"value_src": "default"
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},
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"PHASE": {
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"value": "0.000"
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}
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}
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},
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"rx_sdin_0": {
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"direction": "I"
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},
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"tx_mclk_0": {
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"direction": "O"
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},
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"tx_lrck_0": {
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"direction": "O"
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},
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"tx_sclk_0": {
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"direction": "O"
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},
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"tx_sdout_0": {
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"direction": "O"
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},
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"rx_mclk_0": {
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"direction": "O"
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},
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"rx_lrck_0": {
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"direction": "O"
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},
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"rx_sclk_0": {
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"direction": "O"
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}
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},
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"components": {
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"proc_sys_reset_0": {
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"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
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"xci_name": "loopback_I2S_proc_sys_reset_0_0",
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"xci_path": "ip\\loopback_I2S_proc_sys_reset_0_0\\loopback_I2S_proc_sys_reset_0_0.xci",
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"inst_hier_path": "proc_sys_reset_0",
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"parameters": {
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"RESET_BOARD_INTERFACE": {
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"value": "reset"
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},
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"USE_BOARD_FLOW": {
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"value": "true"
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}
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}
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},
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"clk_wiz_0": {
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"vlnv": "xilinx.com:ip:clk_wiz:6.0",
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"xci_name": "loopback_I2S_clk_wiz_0_0",
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"xci_path": "ip\\loopback_I2S_clk_wiz_0_0\\loopback_I2S_clk_wiz_0_0.xci",
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"inst_hier_path": "clk_wiz_0",
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"parameters": {
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"CLKOUT1_JITTER": {
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"value": "149.337"
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},
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"CLKOUT1_PHASE_ERROR": {
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"value": "122.577"
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},
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"CLKOUT2_JITTER": {
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"value": "201.826"
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},
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"CLKOUT2_PHASE_ERROR": {
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"value": "122.577"
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},
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"CLKOUT2_REQUESTED_OUT_FREQ": {
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"value": "22.579"
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},
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"CLKOUT2_USED": {
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"value": "true"
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},
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"CLK_IN1_BOARD_INTERFACE": {
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"value": "sys_clock"
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},
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"MMCM_CLKFBOUT_MULT_F": {
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"value": "7.000"
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},
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"MMCM_CLKOUT0_DIVIDE_F": {
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"value": "7.000"
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},
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"MMCM_CLKOUT1_DIVIDE": {
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"value": "31"
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},
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"NUM_OUT_CLKS": {
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"value": "2"
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},
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"USE_BOARD_FLOW": {
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"value": "true"
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}
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}
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},
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"proc_sys_reset_1": {
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"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
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"xci_name": "loopback_I2S_proc_sys_reset_0_1",
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"xci_path": "ip\\loopback_I2S_proc_sys_reset_0_1\\loopback_I2S_proc_sys_reset_0_1.xci",
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"inst_hier_path": "proc_sys_reset_1",
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"parameters": {
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"RESET_BOARD_INTERFACE": {
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"value": "reset"
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},
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"USE_BOARD_FLOW": {
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"value": "true"
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}
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}
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},
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"axis_dual_i2s_0": {
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"vlnv": "DigiLAB:ip:axis_dual_i2s:1.0",
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"xci_name": "loopback_I2S_axis_dual_i2s_0_0",
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"xci_path": "ip\\loopback_I2S_axis_dual_i2s_0_0\\loopback_I2S_axis_dual_i2s_0_0.xci",
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"inst_hier_path": "axis_dual_i2s_0"
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},
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"system_ila_0": {
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"vlnv": "xilinx.com:ip:system_ila:1.1",
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"xci_name": "loopback_I2S_system_ila_0_0",
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"xci_path": "ip\\loopback_I2S_system_ila_0_0\\loopback_I2S_system_ila_0_0.xci",
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"inst_hier_path": "system_ila_0",
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"parameters": {
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"C_SLOT_0_INTF_TYPE": {
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"value": "xilinx.com:interface:axis_rtl:1.0"
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}
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},
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"interface_ports": {
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"SLOT_0_AXIS": {
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"mode": "Monitor",
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"vlnv": "xilinx.com:interface:axis_rtl:1.0"
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}
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}
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}
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},
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"interface_nets": {
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"axis_dual_i2s_0_m_axis": {
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"interface_ports": [
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"axis_dual_i2s_0/s_axis",
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"axis_dual_i2s_0/m_axis",
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"system_ila_0/SLOT_0_AXIS"
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]
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}
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},
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"nets": {
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"reset_1": {
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"ports": [
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"reset",
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"proc_sys_reset_0/ext_reset_in",
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"clk_wiz_0/reset",
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"proc_sys_reset_1/ext_reset_in"
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]
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},
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"sys_clock_1": {
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"ports": [
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"sys_clock",
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"clk_wiz_0/clk_in1"
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]
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},
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"clk_wiz_0_locked": {
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"ports": [
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"clk_wiz_0/locked",
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"proc_sys_reset_0/dcm_locked",
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"proc_sys_reset_1/dcm_locked"
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]
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},
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"clk_wiz_0_clk_out1": {
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"ports": [
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"clk_wiz_0/clk_out1",
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"system_ila_0/clk",
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"axis_dual_i2s_0/aclk",
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"proc_sys_reset_0/slowest_sync_clk"
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]
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},
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"clk_wiz_0_clk_out2": {
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"ports": [
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"clk_wiz_0/clk_out2",
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"proc_sys_reset_1/slowest_sync_clk",
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"axis_dual_i2s_0/i2s_clk"
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]
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},
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"proc_sys_reset_0_peripheral_aresetn": {
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"ports": [
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"proc_sys_reset_0/peripheral_aresetn",
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"system_ila_0/resetn",
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"axis_dual_i2s_0/aresetn"
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]
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},
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"proc_sys_reset_1_peripheral_aresetn": {
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"ports": [
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"proc_sys_reset_1/peripheral_aresetn",
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"axis_dual_i2s_0/i2s_resetn"
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]
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},
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"rx_sdin_0_1": {
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"ports": [
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"rx_sdin_0",
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"axis_dual_i2s_0/rx_sdin"
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]
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},
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"axis_dual_i2s_0_tx_mclk": {
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"ports": [
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"axis_dual_i2s_0/tx_mclk",
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"tx_mclk_0"
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]
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},
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"axis_dual_i2s_0_tx_lrck": {
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"ports": [
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"axis_dual_i2s_0/tx_lrck",
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"tx_lrck_0"
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]
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},
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"axis_dual_i2s_0_tx_sclk": {
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"ports": [
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"axis_dual_i2s_0/tx_sclk",
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"tx_sclk_0"
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]
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},
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"axis_dual_i2s_0_tx_sdout": {
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"ports": [
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"axis_dual_i2s_0/tx_sdout",
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"tx_sdout_0"
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]
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},
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"axis_dual_i2s_0_rx_mclk": {
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"ports": [
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"axis_dual_i2s_0/rx_mclk",
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"rx_mclk_0"
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]
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},
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"axis_dual_i2s_0_rx_lrck": {
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"ports": [
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"axis_dual_i2s_0/rx_lrck",
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"rx_lrck_0"
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]
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},
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"axis_dual_i2s_0_rx_sclk": {
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"ports": [
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"axis_dual_i2s_0/rx_sclk",
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"rx_sclk_0"
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]
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}
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}
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}
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} |