Davide cb57866a2e Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust UART interface in uart_viewer.py for enhanced data handling, and modify digilent_jstk2.vhd to remove unnecessary initialization.

2025-05-17 16:16:44 +02:00

..

diligent_jstk.xpr

Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust UART interface in uart_viewer.py for enhanced data handling, and modify digilent_jstk2.vhd to remove unnecessary initialization.

2025-05-17 16:16:44 +02:00