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Update .gitignore and enhance README.md; add new VHDL files for KittCarPWM, ShiftRegisters, and PulseWidthModulator

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This commit is contained in:
Davide Cavagnola
2025-03-20 15:05:27 +01:00
parent c29b83ba63
commit 163ad448f8
23 changed files with 669 additions and 279 deletions
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56
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd
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@@ -1,56 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03.03.2025 14:21:16
-- Design Name:
-- Module Name: shift_register_v0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_register_v0 is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC);
end shift_register_v0;
architecture Behavioral of shift_register_v0 is
signal sr : std_logic := '0';
begin
process(clk, reset)
begin
if reset = '1' then
sr <= '0';
elsif rising_edge(clk) then
sr <= din;
end if;
end process;
dout <= sr;
end Behavioral;

0
LAB0/tb_PulseWidthModulator/tb_PulseWidthModulator.vhd → LAB0/sim/tb_PulseWidthModulator.vhd
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0
LAB0/tb_ShiftRegister/tb_ShiftRegister_v0.vhd → LAB0/sim/tb_ShiftRegister_v0.vhd
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0
LAB0/tb_ShiftRegister/tb_ShiftRegister_v1.vhd → LAB0/sim/tb_ShiftRegister_v1.vhd
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0
LAB0/tb_ShiftRegister/tb_ShiftRegister_v2.vhd → LAB0/sim/tb_ShiftRegister_v2.vhd
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0
LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd → LAB0/src/PulseWidthModulator.vhd
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0
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd → LAB0/src/ShiftRegister_v0.vhd
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0
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd → LAB0/src/ShiftRegister_v1.vhd
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0
LAB0/lab0_shift_register_v2/lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd → LAB0/src/ShiftRegister_v2.vhd
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21
LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr → LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr
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@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr">
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/vivado/lab0_pulse_width_modulator/lab0_pulse_width_modulator.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="5e30cf21c5094cb99e69e33f328f026e"/>
@@ -33,7 +33,7 @@
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
@@ -76,7 +76,7 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/lab0_pulse_width_modulator.vhd">
<File Path="$PPRDIR/../../src/PulseWidthModulator.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -95,7 +95,8 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<File Path="$PPRDIR/../../../Users/david/Downloads/tb_PulseWidthModulator.vhd">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../sim/tb_PulseWidthModulator.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -142,22 +143,18 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>

10
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.xpr → LAB0/vivado/lab0_shift_register_v0/lab0_shift_register_v0.xpr
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@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/lab_0_shift_register/lab_0_shift_register.xpr">
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/vivado/lab0_shift_register_v0/lab0_shift_register_v0.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="79acb559a79942b0a66a9383c435cb5b"/>
@@ -74,7 +74,7 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/ShiftRegister_v0.vhd">
<File Path="$PPRDIR/../../src/ShiftRegister_v0.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -94,7 +94,7 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v0.vhd">
<File Path="$PPRDIR/../../sim/tb_ShiftRegister_v0.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -141,7 +141,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab_0_shift_register/lab_0_shift_register.srcs/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
@@ -150,7 +150,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab_0_shift_register/lab_0_shift_register.srcs/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>

14
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.xpr → LAB0/vivado/lab0_shift_register_v1/lab0_shift_register_v1.xpr
View File

@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/lab0_shift_register_v1/lab0_shift_register_v1.xpr">
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/vivado/lab0_shift_register_v1/lab0_shift_register_v1.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="b6c8e7e1e5944b109219f67e64ef5d5f"/>
@@ -33,7 +33,7 @@
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
@@ -47,7 +47,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="9"/>
<Option Name="WTXSimLaunchSim" Val="10"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -76,7 +76,7 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/ShiftRegister_v1.vhd">
<File Path="$PPRDIR/../../src/ShiftRegister_v1.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -96,7 +96,7 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v1.vhd">
<File Path="$PPRDIR/../../sim/tb_ShiftRegister_v1.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -143,7 +143,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab0_shift_register_v1/lab0_shift_register_v1.srcs/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
@@ -152,7 +152,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab0_shift_register_v1/lab0_shift_register_v1.srcs/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>

23
LAB0/lab0_shift_register_v2/lab0_shift_register_v2.xpr → LAB0/vivado/lab0_shift_register_v2/lab0_shift_register_v2.xpr
View File

@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/lab0_shift_register_v2/lab0_shift_register_v2.xpr">
<Project Version="7" Minor="54" Path="C:/DESD/LAB0/vivado/lab0_shift_register_v2/lab0_shift_register_v2.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="9314b9120ade4657994d00a93c65e94d"/>
@@ -33,7 +33,7 @@
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
@@ -47,7 +47,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="3"/>
<Option Name="WTXSimLaunchSim" Val="4"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -76,7 +76,7 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/ShiftRegister_v2.vhd">
<File Path="$PPRDIR/../../src/ShiftRegister_v2.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -95,7 +95,8 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<File Path="$PPRDIR/../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v2.vhd">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../sim/tb_ShiftRegister_v2.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -142,22 +143,18 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab0_shift_register_v2/lab0_shift_register_v2.srcs/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab0_shift_register_v2/lab0_shift_register_v2.srcs/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>