Update .gitignore and enhance README.md; add new VHDL files for KittCarPWM, ShiftRegisters, and PulseWidthModulator

LAB0/src/PulseWidthModulator.vhd

@@ -0,0 +1,83 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 07.03.2025 15:23:11
+-- Design Name: 
+-- Module Name: PulseWidthModulator - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity PulseWidthModulator is
+    Generic(
+        BIT_LENGTH  : INTEGER RANGE 1 to 16 := 8;
+        T_ON_INIT   : POSITIVE := 64;   
+        PERIOD_INIT : POSITIVE := 128;             
+        PWM_INIT    : STD_LOGIC := '0'
+    );
+    Port (
+        reset   : IN STD_LOGIC;
+        clk     : IN STD_LOGIC;
+        
+        Ton     : IN std_logic_vector(BIT_LENGTH-1 downto 0);
+        Period  : IN std_logic_vector(BIT_LENGTH-1 downto 0);
+        PWM     : OUT std_logic
+    );
+ end PulseWidthModulator;
+
+architecture Behavioral of PulseWidthModulator is
+    signal counter : unsigned(BIT_LENGTH-1 downto 0) := (others => '0');
+    signal pwm_out : std_logic;
+begin
+
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            counter  <= (others => '0');
+            pwm_out  <= '0';  -- Assicura PWM spento al reset
+        elsif rising_edge(clk) then
+            if counter = unsigned(period) then
+                counter <= (others => '0');  -- Reset counter
+            else
+                counter <= counter + 1;  -- Incrementa il counter
+            end if;
+
+            -- Accendi il PWM all'inizio di ogni ciclo
+            if counter = 0 then
+                pwm_out <= '1';  
+            end if;
+
+            -- Spegni il PWM quando il contatore raggiunge Ton
+            if counter = unsigned(Ton) then
+                pwm_out <= '0';
+            end if;
+        end if;
+    end process;
+
+    PWM <= pwm_out; -- Output PWM
+
+end Behavioral;
+

LAB0/src/ShiftRegister_v0.vhd

@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03.03.2025 14:49:43
+-- Design Name: 
+-- Module Name: ShiftRegister_v0 - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ShiftRegister_v0 is
+    Port ( reset : in STD_LOGIC;
+           clk : in STD_LOGIC;
+           din : in STD_LOGIC;
+           dout : out STD_LOGIC);
+end ShiftRegister_v0;
+
+architecture Behavioral of ShiftRegister_v0 is
+    signal sr : std_logic := '0';
+begin
+
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            sr <= '0';
+        elsif rising_edge(clk) then
+            sr <= din;
+        end if;
+    end process;
+    
+    dout <= sr;
+
+end Behavioral;

LAB0/src/ShiftRegister_v1.vhd

@@ -0,0 +1,62 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03.03.2025 15:06:26
+-- Design Name: 
+-- Module Name: ShiftRegister_v1 - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ShiftRegister_v1 is
+    Generic (
+        SR_DEPTH : POSITIVE := 4;
+        SR_INIT : STD_LOGIC := '0'
+    );
+    Port (
+        reset : in STD_LOGIC;
+        clk : in STD_LOGIC;
+        din : in STD_LOGIC;
+        dout : out STD_LOGIC
+    );
+end ShiftRegister_v1;
+
+architecture Behavioral of ShiftRegister_v1 is
+    signal sr : STD_LOGIC_VECTOR(SR_DEPTH-1 DOWNTO 0) := (others => '0');
+begin
+
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            sr <= (others => SR_INIT);
+        elsif rising_edge(clk) then
+            sr <= sr(SR_DEPTH-2 DOWNTO 0) & din;
+        end if;
+    end process;
+    
+    dout <= sr(SR_DEPTH-1);
+
+end Behavioral;

LAB0/src/ShiftRegister_v2.vhd

@@ -0,0 +1,65 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03.03.2025 15:35:08
+-- Design Name: 
+-- Module Name: ShiftRegister_v2 - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ShiftRegister_v2 is
+    Generic (
+        SR_WIDTH : NATURAL := 8;
+        SR_DEPTH : POSITIVE := 4;
+        SR_INIT : STD_LOGIC := '0'
+    );
+    Port (
+        reset : in STD_LOGIC;
+        clk : in STD_LOGIC;
+        din : in STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0);
+        dout : out STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0)
+    );
+end ShiftRegister_v2;
+
+architecture Behavioral of ShiftRegister_v2 is
+    type sr_type is array (SR_DEPTH-1 downto 0) of std_logic_vector(SR_WIDTH-1 downto 0);
+
+    signal sr : sr_type := (others => (others => SR_INIT));
+begin
+
+    process(reset,clk)
+    begin
+        if reset = '1' then
+            sr <= (others => (others => SR_INIT));
+        elsif rising_edge(clk) then
+            sr <= sr(SR_DEPTH-2 downto 0) & din;
+        end if;
+    end process;
+    
+    dout <= sr(SR_DEPTH-1);
+
+end Behavioral;