Refactor packetizer and depacketizer components; update test scripts and images

- Modified the graph structure in pak_depak.bda to correct node and edge connections.
- Adjusted testbench for packetizer (tb_packetizer.vhd) to fix data values and packet sizes.
- Enhanced packetizer.vhd to manage footer sending based on last signal.
- Removed obsolete executable file LAB2-Test_new.exe.
- Updated Python test script (test.py) to include new test case for depack > pack functionality and improved image handling.
- Altered Vivado project files to reflect changes in simulation and synthesis settings.
- Deleted unnecessary test executable and added new image for depack > pack testing.

LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd

@@ -1,8 +1,8 @@
 --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
---Date        : Tue Apr 22 22:40:46 2025
+--Date        : Thu Apr 24 15:46:08 2025
---Host        : Davide-Samsung running 64-bit major release  (build 9200)
+--Host        : DavideASUS running 64-bit major release  (build 9200)
 --Command     : generate_target pak_depak_wrapper.bd
 --Design      : pak_depak_wrapper
 --Purpose     : IP block netlist

LAB2/design/pak_depak/pak_depak.bd

@@ -5,7 +5,7 @@
       "device": "xc7a35tcpg236-1",
       "name": "pak_depak",
       "rev_ctrl_bd_flag": "RevCtrlBdOff",
-      "synth_flow_mode": "None",
+      "synth_flow_mode": "Hierarchical",
       "tool_version": "2020.2",
       "validated": "true"
     },
@@ -13,8 +13,8 @@
       "proc_sys_reset_0": "",
       "clk_wiz_0": "",
       "AXI4Stream_UART_0": "",
-      "packetizer_0": "",
+      "depacketizer_0": "",
-      "depacketizer_0": ""
+      "packetizer_0": ""
     },
     "interface_ports": {
       "usb_uart": {
@@ -78,8 +78,8 @@
       },
       "clk_wiz_0": {
         "vlnv": "xilinx.com:ip:clk_wiz:6.0",
-        "xci_name": "pak_depak_clk_wiz_0_1",
+        "xci_name": "pak_depak_clk_wiz_0_0",
-        "xci_path": "ip\\pak_depak_clk_wiz_0_1\\pak_depak_clk_wiz_0_1.xci",
+        "xci_path": "ip\\pak_depak_clk_wiz_0_0\\pak_depak_clk_wiz_0_0.xci",
         "inst_hier_path": "clk_wiz_0",
         "parameters": {
           "CLK_IN1_BOARD_INTERFACE": {
@@ -107,193 +107,6 @@
           }
         }
       },
-      "packetizer_0": {
-        "vlnv": "xilinx.com:module_ref:packetizer:1.0",
-        "xci_name": "pak_depak_packetizer_0_0",
-        "xci_path": "ip\\pak_depak_packetizer_0_0\\pak_depak_packetizer_0_0.xci",
-        "inst_hier_path": "packetizer_0",
-        "reference_info": {
-          "ref_type": "hdl",
-          "ref_name": "packetizer",
-          "boundary_crc": "0x0"
-        },
-        "interface_ports": {
-          "m_axis": {
-            "mode": "Master",
-            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
-            "parameters": {
-              "TDATA_NUM_BYTES": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "TDEST_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TID_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TUSER_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TREADY": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "HAS_TSTRB": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TKEEP": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TLAST": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "FREQ_HZ": {
-                "value": "100000000",
-                "value_src": "ip_prop"
-              },
-              "PHASE": {
-                "value": "0.0",
-                "value_src": "ip_prop"
-              },
-              "CLK_DOMAIN": {
-                "value": "/clk_wiz_0_clk_out1",
-                "value_src": "ip_prop"
-              }
-            },
-            "port_maps": {
-              "TDATA": {
-                "physical_name": "m_axis_tdata",
-                "direction": "O",
-                "left": "7",
-                "right": "0"
-              },
-              "TVALID": {
-                "physical_name": "m_axis_tvalid",
-                "direction": "O"
-              },
-              "TREADY": {
-                "physical_name": "m_axis_tready",
-                "direction": "I"
-              }
-            }
-          },
-          "s_axis": {
-            "mode": "Slave",
-            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
-            "parameters": {
-              "TDATA_NUM_BYTES": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "TDEST_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TID_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TUSER_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TREADY": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "HAS_TSTRB": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TKEEP": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TLAST": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "FREQ_HZ": {
-                "value": "100000000",
-                "value_src": "ip_prop"
-              },
-              "PHASE": {
-                "value": "0.0",
-                "value_src": "ip_prop"
-              },
-              "CLK_DOMAIN": {
-                "value": "/clk_wiz_0_clk_out1",
-                "value_src": "ip_prop"
-              }
-            },
-            "port_maps": {
-              "TDATA": {
-                "physical_name": "s_axis_tdata",
-                "direction": "I",
-                "left": "7",
-                "right": "0"
-              },
-              "TLAST": {
-                "physical_name": "s_axis_tlast",
-                "direction": "I"
-              },
-              "TVALID": {
-                "physical_name": "s_axis_tvalid",
-                "direction": "I"
-              },
-              "TREADY": {
-                "physical_name": "s_axis_tready",
-                "direction": "O"
-              }
-            }
-          }
-        },
-        "ports": {
-          "clk": {
-            "type": "clk",
-            "direction": "I",
-            "parameters": {
-              "ASSOCIATED_BUSIF": {
-                "value": "m_axis:s_axis",
-                "value_src": "constant"
-              },
-              "ASSOCIATED_RESET": {
-                "value": "aresetn",
-                "value_src": "constant"
-              },
-              "FREQ_HZ": {
-                "value": "100000000",
-                "value_src": "ip_prop"
-              },
-              "PHASE": {
-                "value": "0.0",
-                "value_src": "ip_prop"
-              },
-              "CLK_DOMAIN": {
-                "value": "/clk_wiz_0_clk_out1",
-                "value_src": "ip_prop"
-              }
-            }
-          },
-          "aresetn": {
-            "type": "rst",
-            "direction": "I",
-            "parameters": {
-              "POLARITY": {
-                "value": "ACTIVE_LOW",
-                "value_src": "constant"
-              }
-            }
-          }
-        }
-      },
       "depacketizer_0": {
         "vlnv": "xilinx.com:module_ref:depacketizer:1.0",
         "xci_name": "pak_depak_depacketizer_0_0",
@@ -480,13 +293,200 @@
             }
           }
         }
+      },
+      "packetizer_0": {
+        "vlnv": "xilinx.com:module_ref:packetizer:1.0",
+        "xci_name": "pak_depak_packetizer_0_0",
+        "xci_path": "ip\\pak_depak_packetizer_0_0\\pak_depak_packetizer_0_0.xci",
+        "inst_hier_path": "packetizer_0",
+        "reference_info": {
+          "ref_type": "hdl",
+          "ref_name": "packetizer",
+          "boundary_crc": "0x0"
+        },
+        "interface_ports": {
+          "m_axis": {
+            "mode": "Master",
+            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+            "parameters": {
+              "TDATA_NUM_BYTES": {
+                "value": "1",
+                "value_src": "constant"
+              },
+              "TDEST_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "TID_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "TUSER_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TREADY": {
+                "value": "1",
+                "value_src": "constant"
+              },
+              "HAS_TSTRB": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TKEEP": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TLAST": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "FREQ_HZ": {
+                "value": "100000000",
+                "value_src": "ip_prop"
+              },
+              "PHASE": {
+                "value": "0.0",
+                "value_src": "ip_prop"
+              },
+              "CLK_DOMAIN": {
+                "value": "/clk_wiz_0_clk_out1",
+                "value_src": "ip_prop"
+              }
+            },
+            "port_maps": {
+              "TDATA": {
+                "physical_name": "m_axis_tdata",
+                "direction": "O",
+                "left": "7",
+                "right": "0"
+              },
+              "TVALID": {
+                "physical_name": "m_axis_tvalid",
+                "direction": "O"
+              },
+              "TREADY": {
+                "physical_name": "m_axis_tready",
+                "direction": "I"
+              }
+            }
+          },
+          "s_axis": {
+            "mode": "Slave",
+            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+            "parameters": {
+              "TDATA_NUM_BYTES": {
+                "value": "1",
+                "value_src": "constant"
+              },
+              "TDEST_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "TID_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "TUSER_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TREADY": {
+                "value": "1",
+                "value_src": "constant"
+              },
+              "HAS_TSTRB": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TKEEP": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TLAST": {
+                "value": "1",
+                "value_src": "constant"
+              },
+              "FREQ_HZ": {
+                "value": "100000000",
+                "value_src": "ip_prop"
+              },
+              "PHASE": {
+                "value": "0.0",
+                "value_src": "ip_prop"
+              },
+              "CLK_DOMAIN": {
+                "value": "/clk_wiz_0_clk_out1",
+                "value_src": "ip_prop"
+              }
+            },
+            "port_maps": {
+              "TDATA": {
+                "physical_name": "s_axis_tdata",
+                "direction": "I",
+                "left": "7",
+                "right": "0"
+              },
+              "TLAST": {
+                "physical_name": "s_axis_tlast",
+                "direction": "I"
+              },
+              "TVALID": {
+                "physical_name": "s_axis_tvalid",
+                "direction": "I"
+              },
+              "TREADY": {
+                "physical_name": "s_axis_tready",
+                "direction": "O"
+              }
+            }
+          }
+        },
+        "ports": {
+          "clk": {
+            "type": "clk",
+            "direction": "I",
+            "parameters": {
+              "ASSOCIATED_BUSIF": {
+                "value": "m_axis:s_axis",
+                "value_src": "constant"
+              },
+              "ASSOCIATED_RESET": {
+                "value": "aresetn",
+                "value_src": "constant"
+              },
+              "FREQ_HZ": {
+                "value": "100000000",
+                "value_src": "ip_prop"
+              },
+              "PHASE": {
+                "value": "0.0",
+                "value_src": "ip_prop"
+              },
+              "CLK_DOMAIN": {
+                "value": "/clk_wiz_0_clk_out1",
+                "value_src": "ip_prop"
+              }
+            }
+          },
+          "aresetn": {
+            "type": "rst",
+            "direction": "I",
+            "parameters": {
+              "POLARITY": {
+                "value": "ACTIVE_LOW",
+                "value_src": "constant"
+              }
+            }
+          }
+        }
       }
     },
     "interface_nets": {
-      "AXI4Stream_UART_0_UART": {
+      "AXI4Stream_UART_0_M00_AXIS_RX": {
         "interface_ports": [
-          "usb_uart",
+          "AXI4Stream_UART_0/M00_AXIS_RX",
-          "AXI4Stream_UART_0/UART"
+          "depacketizer_0/s_axis"
         ]
       },
       "depacketizer_0_m_axis": {
@@ -495,17 +495,17 @@
           "packetizer_0/s_axis"
         ]
       },
-      "AXI4Stream_UART_0_M00_AXIS_RX": {
-        "interface_ports": [
-          "AXI4Stream_UART_0/M00_AXIS_RX",
-          "depacketizer_0/s_axis"
-        ]
-      },
       "packetizer_0_m_axis": {
         "interface_ports": [
           "packetizer_0/m_axis",
           "AXI4Stream_UART_0/S00_AXIS_TX"
         ]
+      },
+      "AXI4Stream_UART_0_UART": {
+        "interface_ports": [
+          "usb_uart",
+          "AXI4Stream_UART_0/UART"
+        ]
       }
     },
     "nets": {
@@ -529,8 +529,8 @@
           "proc_sys_reset_0/slowest_sync_clk",
           "AXI4Stream_UART_0/m00_axis_rx_aclk",
           "AXI4Stream_UART_0/s00_axis_tx_aclk",
-          "packetizer_0/clk",
+          "depacketizer_0/clk",
-          "depacketizer_0/clk"
+          "packetizer_0/clk"
         ]
       },
       "proc_sys_reset_0_peripheral_reset": {
@@ -550,8 +550,8 @@
           "proc_sys_reset_0/peripheral_aresetn",
           "AXI4Stream_UART_0/m00_axis_rx_aresetn",
           "AXI4Stream_UART_0/s00_axis_tx_aresetn",
-          "packetizer_0/aresetn",
+          "depacketizer_0/aresetn",
-          "depacketizer_0/aresetn"
+          "packetizer_0/aresetn"
         ]
       }
     }

LAB2/design/pak_depak/pak_depak.bda

@@ -21,22 +21,22 @@
   <key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
   <graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
     <node id="n0">
-      <data key="VM">pak_depak</data>
-      <data key="VT">BC</data>
-    </node>
-    <node id="n1">
       <data key="VH">2</data>
       <data key="VM">pak_depak</data>
       <data key="VT">VR</data>
     </node>
-    <node id="n2">
+    <node id="n1">
       <data key="TU">active</data>
       <data key="VH">2</data>
       <data key="VT">PM</data>
     </node>
-    <edge id="e0" source="n0" target="n1">
+    <node id="n2">
+      <data key="VM">pak_depak</data>
+      <data key="VT">BC</data>
+    </node>
+    <edge id="e0" source="n2" target="n0">
     </edge>
-    <edge id="e1" source="n1" target="n2">
+    <edge id="e1" source="n0" target="n1">
     </edge>
   </graph>
 </graphml>

LAB2/sim/tb_packetizer.vhd

@@ -64,7 +64,7 @@ ARCHITECTURE Behavioral OF tb_packetizer IS
         0 => x"10",
         1 => x"20",
         2 => x"30",
-        3 => x"4",
+        3 => x"04",
         4 => x"54",
         5 => x"65",
         6 => x"73",
@@ -150,12 +150,12 @@ BEGIN
         END LOOP;
         s_axis_tlast <= '0';
 
-        -- Wait a bit, then send another packet of 2 words
+        -- Wait a bit, then send another packet of 1 words
         WAIT FOR 50 ns;
-        FOR i IN 4 TO 5 LOOP
+        FOR i IN 4 TO 4 LOOP
             s_axis_tdata <= mem(i);
             s_axis_tvalid <= '1';
-            IF i = 5 THEN
+            IF i = 4 THEN
                 s_axis_tlast <= '1';
             ELSE
                 s_axis_tlast <= '0';

LAB2/src/packetizer.vhd

@@ -82,8 +82,14 @@ BEGIN
                             m_axis_tdata <= STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)); -- Prepare header
                             m_axis_tvalid_int <= '1'; --Send header
 
+                            IF s_axis_tlast = '1' THEN
+                                s_axis_tready_int <= '0'; -- Block the slave interface to avoid data loss
+                                state <= SENDING_FOOTER;
+                            ELSE
+                                state <= STREAMING;
+                            END IF;
+                            
                             trigger <= '1';
-                            state <= STREAMING;
                         END IF;
 
                     WHEN STREAMING =>
@@ -99,7 +105,7 @@ BEGIN
                     WHEN SENDING_FOOTER =>
                         IF m_axis_tvalid_int = '0' OR m_axis_tready = '1' THEN
                             s_axis_tready_int <= '0'; -- Block the slave interface to avoid data loss
-                            
+
                             data_buffer <= STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)); -- Send footer
                             m_axis_tvalid_int <= '1';
 

LAB2/test/test.py

@@ -1,4 +1,4 @@
-""" import sys
+import sys
 import subprocess
 
 def install_and_import(package, package_name=None):
@@ -16,7 +16,7 @@ install_and_import("serial", "pyserial")
 install_and_import("PIL", "pillow")
 install_and_import("tqdm")
 install_and_import("numpy")
-install_and_import("scipy") """
+install_and_import("scipy")
 
 from serial import Serial
 import serial.tools.list_ports
@@ -30,6 +30,7 @@ IMAGE_UF = r'C:\DESD\LAB2\test\test_uf.png'
 IMAGE_NAME3 = r'C:\DESD\LAB2\test\test3.png'
 IMAGE_NAME2 = r'C:\DESD\LAB2\test\test2.png'
 IMAGE_NAME1 = r'C:\DESD\LAB2\test\test1.png'
+IMAGE_DEPACK_PACK = r'C:\DESD\LAB2\test\test_depack_pack.png'
 
 BASYS3_PID = 0x6010
 BASYS3_VID = 0x0403
@@ -45,17 +46,22 @@ for port in serial.tools.list_ports.comports():
 if not dev:
     raise RuntimeError("Basys 3 Not Found!")
 
-test_n = int(input("Insert test number (1, 2, 3, overflow (4) or underflow (5)): ").strip())
+test_n = int(input("Insert test number (1, 2, 3, 4 (overflow), 5 (underflow) or 6 (depack > pack only)): ").strip())
 
-if test_n not in [1, 2, 3, 4, 5]:
+if test_n not in [1, 2, 3, 4, 5, 6]:
-    raise RuntimeError("Test number must be 1, 2, 3, 4 (overflow) or 5 (underflow)")
+    raise RuntimeError("Test number must be 1, 2, 3, 4 (overflow), 5 (underflow) or 6 (depack > pack only)")
 
 dev = Serial(dev, 115200)
 
-img = Image.open(IMAGE_NAME1 if test_n == 1 else IMAGE_NAME2 if test_n == 2 else IMAGE_NAME3 if test_n == 3 else IMAGE_UF if test_n == 5 else IMAGE_OF)
+img = Image.open(IMAGE_NAME1 if test_n == 1 else IMAGE_NAME2 if test_n == 2 else IMAGE_NAME3 if test_n == 3 else IMAGE_OF if test_n == 4 else IMAGE_UF if test_n == 5 else IMAGE_DEPACK_PACK)
 if img.mode != "RGB":
     img = img.convert("RGB")
 
+if test_n == 4:
+    print("Check for overflow (LED U16)")
+elif test_n == 5:
+    print("Check for underflow (LED U19)")
+
 IMG_WIDTH, IMG_HEIGHT = img.size  # Get dimensions from the image
 
 mat = np.asarray(img, dtype=np.uint8)
@@ -64,39 +70,59 @@ mat = mat[:, :, :3]
 if mat.max() > 127:
     mat = mat // 2
 
-buff = mat.tobytes()
+res = b''
 
-mat_gray = np.sum(mat, axis=2) // 3
+if test_n == 6:
+    print("Check for depack > pack")
 
-sim_img = convolve2d(mat_gray, [[-1, -1, -1], [-1, 8, -1], [-1, -1, -1]], mode="same")
+    total_bytes = IMG_HEIGHT * IMG_WIDTH * 3
+    for idx in tqdm(range(total_bytes)):
+        i = idx // (IMG_WIDTH * 3)
+        j = (idx // 3) % IMG_WIDTH
+        k = idx % 3
 
-sim_img[sim_img < 0] = 0
+        dev.write(b'\xff')
-sim_img[sim_img > 127] = 127
+        dev.write(bytes([mat[i, j, k]]))
-sim_img = sim_img.astype(np.uint8)
+        dev.write(b'\xf1')
+        dev.flush()
 
-dev.write(b'\xff')
+        # Read 3 bytes: header, data, footer
-for i in tqdm(range(IMG_HEIGHT)):
+        resp = dev.read(3)
-    dev.write(buff[i * IMG_WIDTH * 3:(i + 1) * IMG_WIDTH * 3])
+        res += resp[1:2]  # Only keep the data byte
 
-dev.write(b'\xf1')
+    res_img = np.frombuffer(res, dtype=np.uint8)
-dev.flush()
+    res_img = res_img.reshape((IMG_HEIGHT, IMG_WIDTH, 3))
 
-if test_n == 4:
+else:
-    print("Check for overflow (LED U16)")
+    buff = mat.tobytes()
-    exit()
-elif test_n == 5:
-    print("Check for underflow (LED U19)")
-    exit()
 
-res = dev.read(IMG_HEIGHT * IMG_WIDTH + 2)
+    mat_gray = np.sum(mat, axis=2) // 3
 
-res_img = np.frombuffer(res[1:-1], dtype=np.uint8)
+    sim_img = convolve2d(mat_gray, [[-1, -1, -1], [-1, 8, -1], [-1, -1, -1]], mode="same")
-res_img = res_img.reshape((IMG_HEIGHT, IMG_WIDTH))
+
+    sim_img[sim_img < 0] = 0
+    sim_img[sim_img > 127] = 127
+    sim_img = sim_img.astype(np.uint8)
+
+    dev.write(b'\xff')
+    for i in tqdm(range(IMG_HEIGHT)):
+        dev.write(buff[i * IMG_WIDTH * 3:(i + 1) * IMG_WIDTH * 3])
+
+    dev.write(b'\xf1')
+    dev.flush()
+
+    if test_n == 4 or test_n == 5:
+        exit()
+    else:
+        res = dev.read(IMG_HEIGHT * IMG_WIDTH + 2)
+
+    res_img = np.frombuffer(res[1:-1], dtype=np.uint8)
+    res_img = res_img.reshape((IMG_HEIGHT, IMG_WIDTH))
+
+if (test_n == 6 and (res_img == mat).all()) or (res_img == sim_img).all():
+    print("Image Match!")
+else:
+    print("Image Mismatch!")
 
 im = Image.fromarray(res_img)
 im.show()
-
-if np.all(res_img != sim_img):
-    print("Image Mismatch!")
-
-dev.close()

LAB2/vivado/packetizer_test/packetizer_test.xpr

@@ -47,7 +47,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="41"/>
+    <Option Name="WTXSimLaunchSim" Val="45"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -95,6 +95,7 @@
       </Config>
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
       <File Path="$PPRDIR/../../sim/tb_packetizer.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -150,9 +151,7 @@
   <Runs Version="1" Minor="15">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
@@ -161,9 +160,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>

LAB2/vivado/pak_depak/pak_depak.xpr

@@ -55,13 +55,13 @@
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="3"/>
+    <Option Name="WTXSimExportSim" Val="4"/>
-    <Option Name="WTModelSimExportSim" Val="3"/>
+    <Option Name="WTModelSimExportSim" Val="4"/>
-    <Option Name="WTQuestaExportSim" Val="3"/>
+    <Option Name="WTQuestaExportSim" Val="4"/>
-    <Option Name="WTIesExportSim" Val="3"/>
+    <Option Name="WTIesExportSim" Val="4"/>
-    <Option Name="WTVcsExportSim" Val="3"/>
+    <Option Name="WTVcsExportSim" Val="4"/>
-    <Option Name="WTRivieraExportSim" Val="3"/>
+    <Option Name="WTRivieraExportSim" Val="4"/>
-    <Option Name="WTActivehdlExportSim" Val="3"/>
+    <Option Name="WTActivehdlExportSim" Val="4"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -77,13 +77,13 @@
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
-      <File Path="$PPRDIR/../../src/depacketizer.vhd">
+      <File Path="$PPRDIR/../../src/packetizer.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/../../src/packetizer.vhd">
+      <File Path="$PPRDIR/../../src/depacketizer.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
@@ -95,6 +95,21 @@
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
+        <CompFileExtendedInfo CompFileName="pak_depak.bd" FileRelPathName="ip/pak_depak_clk_wiz_0_0/pak_depak_clk_wiz_0_0.xci">
+          <Proxy FileSetName="pak_depak_clk_wiz_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="pak_depak.bd" FileRelPathName="ip/pak_depak_AXI4Stream_UART_0_0/pak_depak_AXI4Stream_UART_0_0.xci">
+          <Proxy FileSetName="pak_depak_AXI4Stream_UART_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="pak_depak.bd" FileRelPathName="ip/pak_depak_proc_sys_reset_0_0/pak_depak_proc_sys_reset_0_0.xci">
+          <Proxy FileSetName="pak_depak_proc_sys_reset_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="pak_depak.bd" FileRelPathName="ip/pak_depak_depacketizer_0_0/pak_depak_depacketizer_0_0.xci">
+          <Proxy FileSetName="pak_depak_depacketizer_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="pak_depak.bd" FileRelPathName="ip/pak_depak_packetizer_0_0/pak_depak_packetizer_0_0.xci">
+          <Proxy FileSetName="pak_depak_packetizer_0_0"/>
+        </CompFileExtendedInfo>
       </File>
       <File Path="$PPRDIR/../../design/pak_depak/hdl/pak_depak_wrapper.vhd">
         <FileInfo>
@@ -137,6 +152,36 @@
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
+    <FileSet Name="pak_depak_proc_sys_reset_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pak_depak_proc_sys_reset_0_0" RelGenDir="$PGENDIR/pak_depak_proc_sys_reset_0_0">
+      <Config>
+        <Option Name="TopModule" Val="pak_depak_proc_sys_reset_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="pak_depak_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pak_depak_clk_wiz_0_0" RelGenDir="$PGENDIR/pak_depak_clk_wiz_0_0">
+      <Config>
+        <Option Name="TopModule" Val="pak_depak_clk_wiz_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="pak_depak_AXI4Stream_UART_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pak_depak_AXI4Stream_UART_0_0" RelGenDir="$PGENDIR/pak_depak_AXI4Stream_UART_0_0">
+      <Config>
+        <Option Name="TopModule" Val="pak_depak_AXI4Stream_UART_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="pak_depak_depacketizer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pak_depak_depacketizer_0_0" RelGenDir="$PGENDIR/pak_depak_depacketizer_0_0">
+      <Config>
+        <Option Name="TopModule" Val="pak_depak_depacketizer_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="pak_depak_packetizer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pak_depak_packetizer_0_0" RelGenDir="$PGENDIR/pak_depak_packetizer_0_0">
+      <Config>
+        <Option Name="TopModule" Val="pak_depak_packetizer_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
   </FileSets>
   <Simulators>
     <Simulator Name="XSim">
@@ -167,6 +212,66 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
+    <Run Id="pak_depak_proc_sys_reset_0_0_synth_1" Type="Ft3:Synth" SrcSet="pak_depak_proc_sys_reset_0_0" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_proc_sys_reset_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pak_depak_proc_sys_reset_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_proc_sys_reset_0_0_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="pak_depak_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="pak_depak_clk_wiz_0_0" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pak_depak_clk_wiz_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_clk_wiz_0_0_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="pak_depak_AXI4Stream_UART_0_0_synth_1" Type="Ft3:Synth" SrcSet="pak_depak_AXI4Stream_UART_0_0" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_AXI4Stream_UART_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pak_depak_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_AXI4Stream_UART_0_0_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="pak_depak_depacketizer_0_0_synth_1" Type="Ft3:Synth" SrcSet="pak_depak_depacketizer_0_0" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_depacketizer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pak_depak_depacketizer_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_depacketizer_0_0_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="pak_depak_packetizer_0_0_synth_1" Type="Ft3:Synth" SrcSet="pak_depak_packetizer_0_0" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_packetizer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pak_depak_packetizer_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_packetizer_0_0_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
@@ -185,6 +290,101 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
+    <Run Id="pak_depak_proc_sys_reset_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_proc_sys_reset_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pak_depak_proc_sys_reset_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_proc_sys_reset_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="pak_depak_clk_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_clk_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pak_depak_clk_wiz_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_clk_wiz_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="pak_depak_AXI4Stream_UART_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_AXI4Stream_UART_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pak_depak_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_AXI4Stream_UART_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="pak_depak_depacketizer_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_depacketizer_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pak_depak_depacketizer_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_depacketizer_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="pak_depak_packetizer_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="pak_depak_packetizer_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pak_depak_packetizer_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/pak_depak_packetizer_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
   </Runs>
   <Board>
     <Jumpers/>