Refactor and optimize various components in LAB3 design

- Updated lab_3.bda to correct node connections and attributes.
- Enhanced LFO.vhd with improved signal handling and clamping logic.
- Modified all_pass_filter.vhd to ensure proper data transfer.
- Adjusted balance_controller.vhd to incorporate reset logic in signal assignments.
- Cleaned up effect_selector.vhd by removing unnecessary assignments.
- Improved led_level_controller.vhd for better readability and functionality.
- Refined moving_average_filter_en.vhd to streamline AXIS assignments.
- Enhanced mute_controller.vhd for clearer data flow management.
- Updated lab3.xpr to correct file paths and simulation settings.

LAB3/design/lab_3/hdl/lab_3_wrapper.vhd

@@ -1,7 +1,7 @@
 --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
---Date        : Mon May 19 16:34:49 2025
+--Date        : Fri May 23 15:41:37 2025
 --Host        : Davide-Samsung running 64-bit major release  (build 9200)
 --Command     : generate_target lab_3_wrapper.bd
 --Design      : lab_3_wrapper
@@ -48,7 +48,6 @@ architecture STRUCTURE of lab_3_wrapper is
     tx_mclk_0 : out STD_LOGIC;
     lfo_enable : in STD_LOGIC;
     effect : in STD_LOGIC;
-    LED : out STD_LOGIC_VECTOR ( 15 downto 0 );
     SPI_M_0_sck_t : out STD_LOGIC;
     SPI_M_0_io1_o : out STD_LOGIC;
     SPI_M_0_ss_t : out STD_LOGIC;
@@ -60,7 +59,8 @@ architecture STRUCTURE of lab_3_wrapper is
     SPI_M_0_sck_o : out STD_LOGIC;
     SPI_M_0_ss_i : in STD_LOGIC;
     SPI_M_0_io1_i : in STD_LOGIC;
-    SPI_M_0_io0_i : in STD_LOGIC
+    SPI_M_0_io0_i : in STD_LOGIC;
+    LED : out STD_LOGIC_VECTOR ( 15 downto 0 )
   );
   end component lab_3;
   component IOBUF is