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This commit is contained in:
Davide Cavagnola
2025-03-18 00:08:53 +01:00
parent 8b2d10725d
commit a73750948c
152 changed files with 3063 additions and 0 deletions
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.gitignore vendored Normal file
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# Vivado-specific files and directories to ignore
# Vivado temporary files
*.jou
*.log
*.str
*.pb
*.wdb
*.xpr
*.xpa
*.backup.*
# Simulation and synthesis-generated files
*.bit
*.bin
*.elf
*.mcs
*.mem
*.prm
*.tsi
*.vcd
*.vdi
*.xml
*.tcl
*.ltx
*.xci
*.dcp
*.xdc
*.xsa
*.xise
*.ngc
*.ngd
*.ncd
*.bgn
*.blf
*.unroutes
*.rpx
*.par
*.twr
*.twx
*.ptwx
*.mrp
*.pcf
*.qpf
*.qsf
*.qws
# Vivado project directories
.sim/
.cache/
.hw/
.hwdbg/
.ip_user_files/
.webtalk/
.xsim/
.xil/
.xilinx/
.xtclsh_history
.fpga_editor.log
.fpga_editor.jou
vivado_pid*.str
vivado*.backup.jou
vivado*.backup.log
# SDK workspace
.sdk/

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LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/gui_handlers.wdf Normal file
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LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/java_command_handlers.wdf Normal file
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3
LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/project.wpc Normal file
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4
LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.cache/wt/xsim.wdf Normal file
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version:1
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eof:241934075

6
LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.hw/lab0_pulse_width_modulator.lpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>

1
LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.ip_user_files/README.txt Normal file
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

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LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/compile.bat Normal file
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@echo off
REM ****************************************************************************
REM Vivado (TM) v2020.2 (64-bit)
REM
REM Filename : compile.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for compiling the simulation design source files
REM
REM Generated by Vivado on Fri Mar 07 17:00:35 +0100 2025
REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
REM
REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
REM
REM usage: compile.bat
REM
REM ****************************************************************************
REM compile VHDL design sources
echo "xvhdl --incr --relax -prj tb_PulseWidthModulator_vhdl.prj"
call xvhdl --incr --relax -prj tb_PulseWidthModulator_vhdl.prj -log xvhdl.log
call type xvhdl.log > compile.log
if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS
:END
exit 1
:SUCCESS
exit 0

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LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/elaborate.bat Normal file
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@echo off
REM ****************************************************************************
REM Vivado (TM) v2020.2 (64-bit)
REM
REM Filename : elaborate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for elaborating the compiled design
REM
REM Generated by Vivado on Fri Mar 07 17:00:38 +0100 2025
REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
REM
REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
REM
REM usage: elaborate.bat
REM
REM ****************************************************************************
REM elaborate design
echo "xelab -wto 5e30cf21c5094cb99e69e33f328f026e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_PulseWidthModulator_behav xil_defaultlib.tb_PulseWidthModulator -log elaborate.log"
call xelab -wto 5e30cf21c5094cb99e69e33f328f026e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_PulseWidthModulator_behav xil_defaultlib.tb_PulseWidthModulator -log elaborate.log
if "%errorlevel%"=="0" goto SUCCESS
if "%errorlevel%"=="1" goto END
:END
exit 1
:SUCCESS
exit 0

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LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/simulate.bat Normal file
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@echo off
REM ****************************************************************************
REM Vivado (TM) v2020.2 (64-bit)
REM
REM Filename : simulate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for simulating the design by launching the simulator
REM
REM Generated by Vivado on Fri Mar 07 17:00:41 +0100 2025
REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
REM
REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
REM
REM usage: simulate.bat
REM
REM ****************************************************************************
REM simulate design
echo "xsim tb_PulseWidthModulator_behav -key {Behavioral:sim_1:Functional:tb_PulseWidthModulator} -tclbatch tb_PulseWidthModulator.tcl -log simulate.log"
call xsim tb_PulseWidthModulator_behav -key {Behavioral:sim_1:Functional:tb_PulseWidthModulator} -tclbatch tb_PulseWidthModulator.tcl -log simulate.log
if "%errorlevel%"=="0" goto SUCCESS
if "%errorlevel%"=="1" goto END
:END
exit 1
:SUCCESS
exit 0

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LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/tb_PulseWidthModulator_vhdl.prj Normal file
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# compile vhdl design source files
vhdl xil_defaultlib \
"../../../../lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd" \
"../../../../../../../Users/david/Downloads/tb_PulseWidthModulator.vhd" \
# Do not sort compile order
nosort

1
LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/Compile_Options.txt Normal file
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-wto "5e30cf21c5094cb99e69e33f328f026e" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "tb_PulseWidthModulator_behav" "xil_defaultlib.tb_PulseWidthModulator" -log "elaborate.log"

1
LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/TempBreakPointFile.txt Normal file
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Breakpoint File Version 1.0

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LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_0.win64.obj Normal file
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LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_1.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_27(char*, char *);
IKI_DLLESPEC extern void execute_28(char*, char *);
IKI_DLLESPEC extern void execute_29(char*, char *);
IKI_DLLESPEC extern void execute_25(char*, char *);
IKI_DLLESPEC extern void execute_26(char*, char *);
IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[7] = {(funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_25, (funcp)execute_26, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 7;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/tb_PulseWidthModulator_behav/xsim.reloc", (void **)funcTab, 7);
iki_vhdl_file_variable_register(dp + 3376);
iki_vhdl_file_variable_register(dp + 3432);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/tb_PulseWidthModulator_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_PulseWidthModulator_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/tb_PulseWidthModulator_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/tb_PulseWidthModulator_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/tb_PulseWidthModulator_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

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5
LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/.xsim_webtallk.info Normal file
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1741361410
1741805296
20
1
5e30cf21c5094cb99e69e33f328f026e

53
LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/webtalk/usage_statistics_ext_xsim.html Normal file
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<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3064766</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Wed Mar 12 19:48:16 2025</TD>
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2020.2 (64-bit)</TD>
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>5e30cf21c5094cb99e69e33f328f026e</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>19</TD>
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>13th Gen Intel(R) Core(TM) i3-1315U</TD>
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2496 MHz</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>command=xsim</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>iteration=2</TD>
<TD>runtime=4 us</TD>
<TD>simulation_memory=8084_KB</TD>
<TD>simulation_time=0.08_sec</TD>
</TR><TR ALIGN='LEFT'> <TD>trace_waveform=true</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
</BODY>
</HTML>

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LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.sim/sim_1/behav/xsim/xsim.dir/tb_PulseWidthModulator_behav/xsim.rlx Normal file
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{
crc : 4590108242048840028 ,
ccp_crc : 0 ,
cmdline : " -wto 5e30cf21c5094cb99e69e33f328f026e --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_PulseWidthModulator_behav xil_defaultlib.tb_PulseWidthModulator" ,
buildDate : "Nov 18 2020" ,
buildTime : "09:47:47" ,
linkCmd : "C:\\Xilinx\\Vivado\\2020.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/tb_PulseWidthModulator_behav/xsimk.exe\" \"xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_0.win64.obj\" \"xsim.dir/tb_PulseWidthModulator_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2020.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" ,
aggregate_nets :
[
]
}

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[General]
ARRAY_DISPLAY_LIMIT=1024
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=65536
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
INPUT_PROTOINST_FILTER=true
OUTPUT_PROTOINST_FILTER=true
INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=75
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
OBJECT_NAME_COLUMN_WIDTH=75
OBJECT_VALUE_COLUMN_WIDTH=75
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
FRAME_INDEX_COLUMN_WIDTH=75
FRAME_NAME_COLUMN_WIDTH=75
FRAME_FILE_NAME_COLUMN_WIDTH=75
FRAME_LINE_NUM_COLUMN_WIDTH=75
LOCAL_NAME_COLUMN_WIDTH=75
LOCAL_VALUE_COLUMN_WIDTH=75
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
PROTO_NAME_COLUMN_WIDTH=0
PROTO_VALUE_COLUMN_WIDTH=0
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1

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0.7
2020.2
Nov 18 2020
09:47:47
C:/DESD/LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd,1741363223,vhdl,,,,pulsewidthmodulator,,,,,,,,
C:/Users/david/Downloads/tb_PulseWidthModulator.vhd,1741361906,vhdl,,,,tb_pulsewidthmodulator,,,,,,,,

1
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xil_defaultlib=xsim.dir/xil_defaultlib

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.03.2025 15:23:11
-- Design Name:
-- Module Name: PulseWidthModulator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PulseWidthModulator is
Generic(
BIT_LENGTH : INTEGER RANGE 1 to 16 := 8;
T_ON_INIT : POSITIVE := 64;
PERIOD_INIT : POSITIVE := 128;
PWM_INIT : STD_LOGIC := '0'
);
Port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
Ton : IN std_logic_vector(BIT_LENGTH-1 downto 0);
Period : IN std_logic_vector(BIT_LENGTH-1 downto 0);
PWM : OUT std_logic
);
end PulseWidthModulator;
architecture Behavioral of PulseWidthModulator is
signal counter : unsigned(BIT_LENGTH-1 downto 0) := (others => '0');
signal pwm_out : std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
counter <= (others => '0');
pwm_out <= '0'; -- Assicura PWM spento al reset
elsif rising_edge(clk) then
if counter = unsigned(period) then
counter <= (others => '0'); -- Reset counter
else
counter <= counter + 1; -- Incrementa il counter
end if;
-- Accendi il PWM all'inizio di ogni ciclo
if counter = 0 then
pwm_out <= '1';
end if;
-- Spegni il PWM quando il contatore raggiunge Ton
if counter = unsigned(Ton) then
pwm_out <= '0';
end if;
end if;
end process;
PWM <= pwm_out; -- Output PWM
end Behavioral;

23
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73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
eof:3126106825

4
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.cache/wt/xsim.wdf Normal file
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@@ -0,0 +1,4 @@
version:1
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
eof:241934075

6
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.hw/lab0_shift_register_v0.lpr Normal file
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@@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>

1
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.ip_user_files/README.txt Normal file
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@@ -0,0 +1 @@
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

26
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/compile.bat Normal file
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@@ -0,0 +1,26 @@
@echo off
REM ****************************************************************************
REM Vivado (TM) v2020.2 (64-bit)
REM
REM Filename : compile.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for compiling the simulation design source files
REM
REM Generated by Vivado on Mon Mar 03 14:57:07 +0100 2025
REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
REM
REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
REM
REM usage: compile.bat
REM
REM ****************************************************************************
REM compile VHDL design sources
echo "xvhdl --incr --relax -prj tb_ShiftRegister_v0_vhdl.prj"
call xvhdl --incr --relax -prj tb_ShiftRegister_v0_vhdl.prj -log xvhdl.log
call type xvhdl.log > compile.log
if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS
:END
exit 1
:SUCCESS
exit 0

25
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/elaborate.bat Normal file
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@@ -0,0 +1,25 @@
@echo off
REM ****************************************************************************
REM Vivado (TM) v2020.2 (64-bit)
REM
REM Filename : elaborate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for elaborating the compiled design
REM
REM Generated by Vivado on Mon Mar 03 14:57:09 +0100 2025
REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
REM
REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
REM
REM usage: elaborate.bat
REM
REM ****************************************************************************
REM elaborate design
echo "xelab -wto 79acb559a79942b0a66a9383c435cb5b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v0_behav xil_defaultlib.tb_ShiftRegister_v0 -log elaborate.log"
call xelab -wto 79acb559a79942b0a66a9383c435cb5b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v0_behav xil_defaultlib.tb_ShiftRegister_v0 -log elaborate.log
if "%errorlevel%"=="0" goto SUCCESS
if "%errorlevel%"=="1" goto END
:END
exit 1
:SUCCESS
exit 0

6
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/shift_register_v0_v0_vhdl.prj Normal file
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@@ -0,0 +1,6 @@
# compile vhdl design source files
vhdl xil_defaultlib \
"../../../../lab_0_shift_register.srcs/sources_1/new/shift_register_v0.vhd" \
# Do not sort compile order
nosort

25
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/simulate.bat Normal file
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@@ -0,0 +1,25 @@
@echo off
REM ****************************************************************************
REM Vivado (TM) v2020.2 (64-bit)
REM
REM Filename : simulate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for simulating the design by launching the simulator
REM
REM Generated by Vivado on Mon Mar 03 14:57:16 +0100 2025
REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
REM
REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
REM
REM usage: simulate.bat
REM
REM ****************************************************************************
REM simulate design
echo "xsim tb_ShiftRegister_v0_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v0} -tclbatch tb_ShiftRegister_v0.tcl -log simulate.log"
call xsim tb_ShiftRegister_v0_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v0} -tclbatch tb_ShiftRegister_v0.tcl -log simulate.log
if "%errorlevel%"=="0" goto SUCCESS
if "%errorlevel%"=="1" goto END
:END
exit 1
:SUCCESS
exit 0

7
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/tb_ShiftRegister_v0_vhdl.prj Normal file
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@@ -0,0 +1,7 @@
# compile vhdl design source files
vhdl xil_defaultlib \
"../../../../lab_0_shift_register.srcs/sources_1/new/ShiftRegister_v0.vhd" \
"../../../../../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v0.vhd" \
# Do not sort compile order
nosort

1
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/Compile_Options.txt Normal file
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@@ -0,0 +1 @@
-wto "79acb559a79942b0a66a9383c435cb5b" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "shift_register_v0_behav" "xil_defaultlib.shift_register_v0" -log "elaborate.log"

1
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/TempBreakPointFile.txt Normal file
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@@ -0,0 +1 @@
Breakpoint File Version 1.0

BIN
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_0.win64.obj Normal file
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109
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_1.c Normal file
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@@ -0,0 +1,109 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_8(char*, char *);
IKI_DLLESPEC extern void execute_9(char*, char *);
IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[4] = {(funcp)execute_8, (funcp)execute_9, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 4;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/shift_register_v0_behav/xsim.reloc", (void **)funcTab, 4);
iki_vhdl_file_variable_register(dp + 2688);
iki_vhdl_file_variable_register(dp + 2744);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/shift_register_v0_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/shift_register_v0_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/shift_register_v0_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/shift_register_v0_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/shift_register_v0_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

BIN
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/obj/xsim_1.win64.obj Normal file
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5
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/.xsim_webtallk.info Normal file
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@@ -0,0 +1,5 @@
1741009327
0
2
1
79acb559a79942b0a66a9383c435cb5b

63
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.html Normal file
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@@ -0,0 +1,63 @@
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3064766</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Mar 3 14:42:07 2025</TD>
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2020.2 (64-bit)</TD>
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>79acb559a79942b0a66a9383c435cb5b</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>1</TD>
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>13th Gen Intel(R) Core(TM) i3-1315U</TD>
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2496 MHz</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>command=xelab</TD>
<TD>debug=typical</TD>
<TD>dpi_used=false</TD>
<TD>file_counter=5</TD>
</TR><TR ALIGN='LEFT'> <TD>gendll=false</TD>
<TD>hwcosim=false</TD>
<TD>sdfmodeling=false</TD>
<TD>vhdl2008=false</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>compiler_memory=58596_KB</TD>
<TD>compiler_time=0.45_sec</TD>
<TD>simulation_image_code=62 KB</TD>
<TD>simulation_image_data=2 KB</TD>
</TR><TR ALIGN='LEFT'> <TD>total_instances=4</TD>
<TD>total_nets=0</TD>
<TD>total_processes=2</TD>
<TD>xilinx_hdl_libraries_used=secureip </TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
</BODY>
</HTML>

38
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/webtalk/usage_statistics_ext_xsim.wdm Normal file
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@@ -0,0 +1,38 @@
version = "1.0";
clients =
(
{ client_name = "project";
rules = (
{
context="software_version_and_target_device";
xml_map="software_version_and_target_device";
html_map="software_version_and_target_device";
html_format="UserEnvStyle";
},
{
context="user_environment";
xml_map="user_environment";
html_map="user_environment";
html_format="UserEnvStyle";
}
);
},
{ client_name = "xsim";
rules = (
{
context="xsim\\command_line_options";
xml_map="xsim\\command_line_options";
html_map="xsim\\command_line_options";
html_format="UnisimStatsStyle";
},
{
context="xsim\\usage";
xml_map="xsim\\usage";
html_map="xsim\\usage";
html_format="UnisimStatsStyle";
}
);
}
);

BIN
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.dbg Normal file
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LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.reloc Normal file
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12
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/shift_register_v0_v0_behav/xsim.rlx Normal file
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@@ -0,0 +1,12 @@
{
crc : 14328939556394471054 ,
ccp_crc : 0 ,
cmdline : " -wto 79acb559a79942b0a66a9383c435cb5b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot shift_register_v0_behav xil_defaultlib.shift_register_v0" ,
buildDate : "Nov 18 2020" ,
buildTime : "09:47:47" ,
linkCmd : "C:\\Xilinx\\Vivado\\2020.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/shift_register_v0_behav/xsimk.exe\" \"xsim.dir/shift_register_v0_behav/obj/xsim_0.win64.obj\" \"xsim.dir/shift_register_v0_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2020.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" ,
aggregate_nets :
[
]
}

BIN
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1
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/Compile_Options.txt Normal file
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@@ -0,0 +1 @@
-wto "79acb559a79942b0a66a9383c435cb5b" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "tb_ShiftRegister_v0_behav" "xil_defaultlib.tb_ShiftRegister_v0" -log "elaborate.log"

1
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/TempBreakPointFile.txt Normal file
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@@ -0,0 +1 @@
Breakpoint File Version 1.0

BIN
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_0.win64.obj Normal file
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112
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.c Normal file
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@@ -0,0 +1,112 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_13(char*, char *);
IKI_DLLESPEC extern void execute_14(char*, char *);
IKI_DLLESPEC extern void execute_15(char*, char *);
IKI_DLLESPEC extern void execute_11(char*, char *);
IKI_DLLESPEC extern void execute_12(char*, char *);
IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[7] = {(funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_11, (funcp)execute_12, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 7;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/tb_ShiftRegister_v0_behav/xsim.reloc", (void **)funcTab, 7);
iki_vhdl_file_variable_register(dp + 2864);
iki_vhdl_file_variable_register(dp + 2920);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/tb_ShiftRegister_v0_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_ShiftRegister_v0_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/tb_ShiftRegister_v0_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/tb_ShiftRegister_v0_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/tb_ShiftRegister_v0_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

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LAB0/lab0_shift_register_v0/lab0_shift_register_v0.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v0_behav/webtalk/.xsim_webtallk.info Normal file
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1741010234
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3
1
79acb559a79942b0a66a9383c435cb5b

53
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<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3064766</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Mar 3 15:05:20 2025</TD>
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2020.2 (64-bit)</TD>
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>79acb559a79942b0a66a9383c435cb5b</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>2</TD>
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>13th Gen Intel(R) Core(TM) i3-1315U</TD>
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2496 MHz</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>command=xsim</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>iteration=1</TD>
<TD>runtime=1 us</TD>
<TD>simulation_memory=8980_KB</TD>
<TD>simulation_time=0.01_sec</TD>
</TR><TR ALIGN='LEFT'> <TD>trace_waveform=true</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
</BODY>
</HTML>

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{
crc : 9168915969947038954 ,
ccp_crc : 0 ,
cmdline : " -wto 79acb559a79942b0a66a9383c435cb5b --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v0_behav xil_defaultlib.tb_ShiftRegister_v0" ,
buildDate : "Nov 18 2020" ,
buildTime : "09:47:47" ,
linkCmd : "C:\\Xilinx\\Vivado\\2020.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/tb_ShiftRegister_v0_behav/xsimk.exe\" \"xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_0.win64.obj\" \"xsim.dir/tb_ShiftRegister_v0_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2020.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" ,
aggregate_nets :
[
]
}

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[General]
ARRAY_DISPLAY_LIMIT=1024
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=65536
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
INPUT_PROTOINST_FILTER=true
OUTPUT_PROTOINST_FILTER=true
INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=75
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
OBJECT_NAME_COLUMN_WIDTH=75
OBJECT_VALUE_COLUMN_WIDTH=75
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
FRAME_INDEX_COLUMN_WIDTH=75
FRAME_NAME_COLUMN_WIDTH=75
FRAME_FILE_NAME_COLUMN_WIDTH=75
FRAME_LINE_NUM_COLUMN_WIDTH=75
LOCAL_NAME_COLUMN_WIDTH=75
LOCAL_VALUE_COLUMN_WIDTH=75
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
PROTO_NAME_COLUMN_WIDTH=0
PROTO_VALUE_COLUMN_WIDTH=0
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1

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0.7
2020.2
Nov 18 2020
09:47:47
C:/DESD/LAB0/lab_0_shift_register/lab_0_shift_register.srcs/sources_1/new/ShiftRegister_v0.vhd,1741010016,vhdl,,,,shiftregister_v0,,,,,,,,
C:/DESD/LAB0/lab_0_shift_register/lab_0_shift_register.srcs/sources_1/new/shift_register_v0.vhd,1741009257,vhdl,,,,shift_register_v0,,,,,,,,
C:/Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v0.vhd,1741009565,vhdl,,,,tb_shiftregister_v0,,,,,,,,

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xil_defaultlib=xsim.dir/xil_defaultlib

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03.03.2025 14:49:43
-- Design Name:
-- Module Name: ShiftRegister_v0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ShiftRegister_v0 is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC);
end ShiftRegister_v0;
architecture Behavioral of ShiftRegister_v0 is
signal sr : std_logic := '0';
begin
process(clk, reset)
begin
if reset = '1' then
sr <= '0';
elsif rising_edge(clk) then
sr <= din;
end if;
end process;
dout <= sr;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03.03.2025 14:21:16
-- Design Name:
-- Module Name: shift_register_v0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_register_v0 is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC);
end shift_register_v0;
architecture Behavioral of shift_register_v0 is
signal sr : std_logic := '0';
begin
process(clk, reset)
begin
if reset = '1' then
sr <= '0';
elsif rising_edge(clk) then
sr <= din;
end if;
end process;
dout <= sr;
end Behavioral;

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3
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/project.wpc Normal file
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version:1
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eof:

4
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.cache/wt/xsim.wdf Normal file
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version:1
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7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
eof:241934075

6
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.hw/lab0_shift_register_v1.lpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>

1
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.ip_user_files/README.txt Normal file
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

26
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/compile.bat Normal file
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@echo off
REM ****************************************************************************
REM Vivado (TM) v2020.2 (64-bit)
REM
REM Filename : compile.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for compiling the simulation design source files
REM
REM Generated by Vivado on Mon Mar 03 15:31:33 +0100 2025
REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
REM
REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
REM
REM usage: compile.bat
REM
REM ****************************************************************************
REM compile VHDL design sources
echo "xvhdl --incr --relax -prj tb_ShiftRegister_v1_vhdl.prj"
call xvhdl --incr --relax -prj tb_ShiftRegister_v1_vhdl.prj -log xvhdl.log
call type xvhdl.log > compile.log
if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS
:END
exit 1
:SUCCESS
exit 0

25
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/elaborate.bat Normal file
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@echo off
REM ****************************************************************************
REM Vivado (TM) v2020.2 (64-bit)
REM
REM Filename : elaborate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for elaborating the compiled design
REM
REM Generated by Vivado on Mon Mar 03 15:31:34 +0100 2025
REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
REM
REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
REM
REM usage: elaborate.bat
REM
REM ****************************************************************************
REM elaborate design
echo "xelab -wto b6c8e7e1e5944b109219f67e64ef5d5f --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v1_behav xil_defaultlib.tb_ShiftRegister_v1 -log elaborate.log"
call xelab -wto b6c8e7e1e5944b109219f67e64ef5d5f --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot tb_ShiftRegister_v1_behav xil_defaultlib.tb_ShiftRegister_v1 -log elaborate.log
if "%errorlevel%"=="0" goto SUCCESS
if "%errorlevel%"=="1" goto END
:END
exit 1
:SUCCESS
exit 0

25
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/simulate.bat Normal file
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@echo off
REM ****************************************************************************
REM Vivado (TM) v2020.2 (64-bit)
REM
REM Filename : simulate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for simulating the design by launching the simulator
REM
REM Generated by Vivado on Mon Mar 03 15:31:36 +0100 2025
REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
REM
REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
REM
REM usage: simulate.bat
REM
REM ****************************************************************************
REM simulate design
echo "xsim tb_ShiftRegister_v1_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v1} -tclbatch tb_ShiftRegister_v1.tcl -log simulate.log"
call xsim tb_ShiftRegister_v1_behav -key {Behavioral:sim_1:Functional:tb_ShiftRegister_v1} -tclbatch tb_ShiftRegister_v1.tcl -log simulate.log
if "%errorlevel%"=="0" goto SUCCESS
if "%errorlevel%"=="1" goto END
:END
exit 1
:SUCCESS
exit 0

7
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/tb_ShiftRegister_v1_vhdl.prj Normal file
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# compile vhdl design source files
vhdl xil_defaultlib \
"../../../../lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd" \
"../../../../../../../Users/david/Downloads/tb_ShiftRegister/tb_ShiftRegister_v1.vhd" \
# Do not sort compile order
nosort

1
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/Compile_Options.txt Normal file
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-wto "b6c8e7e1e5944b109219f67e64ef5d5f" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "tb_ShiftRegister_v1_behav" "xil_defaultlib.tb_ShiftRegister_v1" -log "elaborate.log"

1
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/TempBreakPointFile.txt Normal file
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Breakpoint File Version 1.0

BIN
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_0.win64.obj Normal file
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112
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_13(char*, char *);
IKI_DLLESPEC extern void execute_14(char*, char *);
IKI_DLLESPEC extern void execute_15(char*, char *);
IKI_DLLESPEC extern void execute_11(char*, char *);
IKI_DLLESPEC extern void execute_12(char*, char *);
IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[7] = {(funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_11, (funcp)execute_12, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 7;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/tb_ShiftRegister_v1_behav/xsim.reloc", (void **)funcTab, 7);
iki_vhdl_file_variable_register(dp + 2864);
iki_vhdl_file_variable_register(dp + 2920);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/tb_ShiftRegister_v1_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_ShiftRegister_v1_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/tb_ShiftRegister_v1_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/tb_ShiftRegister_v1_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/tb_ShiftRegister_v1_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

BIN
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/obj/xsim_1.win64.obj Normal file
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5
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/.xsim_webtallk.info Normal file
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1741012152
1741012195
5
1
b6c8e7e1e5944b109219f67e64ef5d5f

53
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.sim/sim_1/behav/xsim/xsim.dir/tb_ShiftRegister_v1_behav/webtalk/usage_statistics_ext_xsim.html Normal file
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<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3064766</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Mar 3 15:29:55 2025</TD>
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2020.2 (64-bit)</TD>
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>b6c8e7e1e5944b109219f67e64ef5d5f</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>2</TD>
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>206ae858-3376-4470-a498-c3cf687aa829</TD>
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>13th Gen Intel(R) Core(TM) i3-1315U</TD>
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2496 MHz</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>command=xsim</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>iteration=0</TD>
<TD>runtime=110 ns</TD>
<TD>simulation_memory=8996_KB</TD>
<TD>simulation_time=0.00_sec</TD>
</TR><TR ALIGN='LEFT'> <TD>trace_waveform=true</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
</BODY>
</HTML>

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