Commit Graph

9 Commits

Author SHA1 Message Date
835b4d0ab8 Refactor and update various components in LAB2 design
- Updated node connections in lab_2.bda and pak_depak.bda to correct source and target references.
- Modified pak_depak_wrapper.vhd to reflect the correct timestamp.
- Rearranged the order of components in pak_depak.bd for clarity and consistency.
- Adjusted BRAM writer logic in bram_writer.vhd for improved data handling and comments for clarity.
- Enhanced depacketizer.vhd with additional comments and logic adjustments for better data reception.
- Refined divider_by_3.vhd to optimize division calculations and improve clarity in comments.
- Improved img_conv.vhd with better state management and comments for the convolution process.
- Updated led_blinker.vhd to enhance readability and maintainability with clearer comments.
- Enhanced packetizer.vhd to improve data handling and added comments for better understanding.
- Adjusted rgb2gray.vhd to include standard library comments for consistency.
- Updated test.py to improve image processing logic and added visualization for differences.
- Added new binary files for test_nopath.exe and archived project files for lab2 and pak_depak.
- Updated Vivado project files to ensure correct paths and settings for synthesis and implementation.
2025-04-25 00:43:10 +02:00
722b479811 Create design folder and update projects 2025-04-22 22:56:28 +02:00
f014f8c341 Refactor and clean up project files
- Removed obsolete GraphML file `pak_depak.bda` and UI file `bd_c9b29a54.ui`.
- Updated `rgb2gray.vhd` to improve signal handling and state machine logic.
- Created new Vivado project files for `depacketizer_test`, including testbench configuration.
- Adjusted `pak_depak.xpr` to disable the FIFO module and set the top module correctly.
- Updated `rgb2grey_test.xpr` to modify simulation launch settings.
2025-04-22 22:32:01 +02:00
cd5d1b8a0c Add new AXI4-Stream UART IP and update .gitignore for Lab2 files 2025-03-31 18:35:29 +02:00
163ad448f8 Update .gitignore and enhance README.md; add new VHDL files for KittCarPWM, ShiftRegisters, and PulseWidthModulator 2025-03-20 15:05:27 +01:00
9e8805b4e5 add .xpr 2025-03-18 09:57:38 +01:00
2a88d406f8 commit 2025-03-18 00:21:11 +01:00
4e1e66a5e4 commit 2025-03-18 00:16:41 +01:00
a73750948c second commit 2025-03-18 00:08:53 +01:00