Cd16d c99622188d Update design files for LAB3: reorganize components and adjust simulation settings

2025-05-12 14:38:11 +02:00

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cons

Reorder reset, sys_clock and USB UART ports in lab_2_wrapper and update synthesis flow mode in lab_2.bd

2025-04-09 11:40:21 +02:00

design

Update design files for LAB3: reorganize components and adjust simulation settings

2025-05-12 14:38:11 +02:00

ip/AXI4-Stream_UART

Add new AXI4-Stream UART IP and update .gitignore for Lab2 files

2025-03-31 18:35:29 +02:00

sim

Refactor packetizer and depacketizer components; update test scripts and images

2025-04-24 17:23:56 +02:00

src

Update design files: modify timestamps, enhance signal connections, and improve comments for clarity; remove archived project files

2025-04-25 22:18:03 +02:00

test

Remove .exe too big for Github

2025-04-25 23:02:55 +02:00

vivado

Update design files for LAB3: reorganize components and adjust simulation settings

2025-05-12 14:38:11 +02:00