Block a user
6cb0e4095e
Add moving average filter testbench and configuration files; refactor signal handling in filter components
d3dd458825
Update volume_multiplier testbench and adjust simulation settings; refactor balance_controller and effect_selector logic
fd7bac0da1
Refactor balance_controller and volume_multiplier for improved readability; update simulation settings in project files
Lab 3: Audio Processing System
4e3d7c45a2
Add Vivado project files and testbench configurations for volume multiplier and volume saturator
1b6bae5183
Refactor volume_saturator VHDL code for improved readability and structure; update project files for consistent path references and disable unused components in lab3 design.
5f30651763
Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust node connections in diligent_jstk.bda, and modify delay parameter in digilent_jstk2.vhd for improved functionality and performance.
6ab3f7bcde
Refactor LFO and design files: update LFO entity parameters, adjust signal handling, and modify project file paths for improved functionality and organization.
be88f69202
Refactor LFO, all_pass_filter, and moving_average_filter: enhance output assignments, improve data handling, and streamline signal processing logic for better performance and maintainability.
cb57866a2e
Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust UART interface in uart_viewer.py for enhanced data handling, and modify digilent_jstk2.vhd to remove unnecessary initialization.
1eb2181d1d
Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.
8fd7db7575
Refactor diligent_jstk design files: update clock wizard paths, modify interface nets, enhance uart_viewer.py for real-time data visualization, and remove unused Vivado project zip file.
460378cdaa
Update digilent_jstk2.vhd to clarify the required packet delay for SPI IP-Core functionality
55c5c84247
Refactor lab_3.bda to update node IDs and edge connections; modify digilent_jstk2.vhd to increase packet delay and adjust state machine; enhance uart_viewer.py for real-time coordinate visualization using matplotlib; update diligent_jstk.xpr simulation settings and remove unused file sets; add new Vivado project zip files for diligent_jstk and lab3.