Davide Cavagnola PickleRick
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  • Joined on 2025-03-14
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PickleRick pushed to LAB3 at PickleRick/DESD 2025-05-17 16:16:58 +02:00
cb57866a2e Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust UART interface in uart_viewer.py for enhanced data handling, and modify digilent_jstk2.vhd to remove unnecessary initialization.
PickleRick pushed to LAB3 at PickleRick/DESD 2025-05-17 13:29:55 +02:00
1eb2181d1d Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.
PickleRick pushed to LAB3 at PickleRick/DESD 2025-05-16 22:49:41 +02:00
8fd7db7575 Refactor diligent_jstk design files: update clock wizard paths, modify interface nets, enhance uart_viewer.py for real-time data visualization, and remove unused Vivado project zip file.
PickleRick pushed to LAB3 at PickleRick/DESD 2025-05-16 16:44:50 +02:00
460378cdaa Update digilent_jstk2.vhd to clarify the required packet delay for SPI IP-Core functionality
PickleRick pushed to LAB3 at PickleRick/DESD 2025-05-16 16:43:58 +02:00
55c5c84247 Refactor lab_3.bda to update node IDs and edge connections; modify digilent_jstk2.vhd to increase packet delay and adjust state machine; enhance uart_viewer.py for real-time coordinate visualization using matplotlib; update diligent_jstk.xpr simulation settings and remove unused file sets; add new Vivado project zip files for diligent_jstk and lab3.
PickleRick pushed to LAB3 at PickleRick/DESD 2025-05-15 16:46:23 +02:00
c3967c3124 Update VHDL and Python files for improved functionality and performance
PickleRick pushed to LAB3 at PickleRick/DESD 2025-05-14 14:34:36 +02:00
aa8d8f3c7c Refactor design files for LAB3: update diligent_jstk and add testbench for digilent_jstk2
PickleRick pushed to LAB3 at PickleRick/DESD 2025-05-12 18:30:52 +02:00
PickleRick created branch LAB3 in PickleRick/DESD 2025-05-12 18:30:52 +02:00
PickleRick pushed to main at PickleRick/DESD 2025-05-12 18:17:11 +02:00
b11c65043f Add AXI4-Stream UART IP and associated files
PickleRick deleted branch LAB3 from PickleRick/DESD 2025-05-12 15:01:16 +02:00
PickleRick created branch LAB3 in PickleRick/DESD 2025-05-12 15:00:27 +02:00
PickleRick pushed to LAB3 at PickleRick/DESD 2025-05-12 15:00:27 +02:00
PickleRick deleted branch LAB3 from PickleRick/DESD 2025-05-12 14:59:25 +02:00
PickleRick pushed to main at PickleRick/DESD 2025-05-12 14:58:10 +02:00
a4ec7ce43a Add lab_3_wrapper VHDL file and update project files for LAB3
PickleRick created branch LAB3 in PickleRick/DESD 2025-05-12 14:40:23 +02:00
PickleRick pushed to LAB3 at PickleRick/DESD 2025-05-12 14:40:23 +02:00
PickleRick deleted branch LAB3 from PickleRick/DESD 2025-05-12 14:38:59 +02:00
PickleRick merged pull request PickleRick/DESD#2 2025-05-12 14:38:52 +02:00
LAB3 - setup
PickleRick pushed to main at PickleRick/DESD 2025-05-12 14:38:52 +02:00
3b3096d968 Merge pull request 'LAB3 - setup' (#2) from LAB3 into main
c99622188d Update design files for LAB3: reorganize components and adjust simulation settings
60a8aa912d Add initial design files and project configuration for LAB3
079d1ab0d5 Add IPs
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