Commit Graph

8 Commits

Author SHA1 Message Date
c712b160cc Refactor RGB to Grayscale conversion: update divider component and add testbench 2025-04-11 13:00:46 +02:00
0d805b93b6 Refactor RGB to Grayscale Converter and Add Divider Component
- Updated the rgb2gray.vhd file to improve readability and structure, including consistent casing for keywords and signals.
- Implemented a new divider_by_3 component to calculate the grayscale value by dividing the sum of RGB channels by 3.
- Enhanced the state machine in rgb2gray to handle RGB input and output grayscale values correctly.
- Updated the Vivado project file to include the new divider_by_3.vhd for synthesis and simulation.
- Modified vhdl_ls.toml to include unisim files for third-party library support.
2025-04-11 01:50:19 +02:00
0912887822 TEMP Implement state machine in packetizer for improved packet handling 2025-04-09 12:59:00 +02:00
1e84f090b7 Implement state machine in depacketizer for packet processing and add top auto-set option in project configuration 2025-04-09 12:52:28 +02:00
360ae72198 Reorder reset, sys_clock and USB UART ports in lab_2_wrapper and update synthesis flow mode in lab_2.bd 2025-04-09 11:40:21 +02:00
cd5d1b8a0c Add new AXI4-Stream UART IP and update .gitignore for Lab2 files 2025-03-31 18:35:29 +02:00
a5264642a6 Add new VHDL entities for image processing and update test scripts for Lab2 2025-03-29 00:50:32 +01:00
163ad448f8 Update .gitignore and enhance README.md; add new VHDL files for KittCarPWM, ShiftRegisters, and PulseWidthModulator 2025-03-20 15:05:27 +01:00