Commit Graph

18 Commits

Author SHA1 Message Date
31f66ef8d1 Update design files: modify timestamps, enhance signal connections, and improve comments for clarity; remove archived project files 2025-04-25 22:18:03 +02:00
14a6be00d6 Add loopback design files and update project configurations
- Created a new loopback design file (loopback.bda) with nodes and edges defined in GraphML format.
- Added a new Vivado project file for loopback (loopback.xpr) with updated configurations.
- Introduced a new testbench for image convolution (img_conv_tb.vhd) in the simulation sources.
- Updated the main project file (lab2.xpr) to reflect changes in source files and top module for simulation.
- Removed obsolete project files (pak_depak.xpr.zip) and updated paths for existing source files.
2025-04-25 11:16:54 +02:00
835b4d0ab8 Refactor and update various components in LAB2 design
- Updated node connections in lab_2.bda and pak_depak.bda to correct source and target references.
- Modified pak_depak_wrapper.vhd to reflect the correct timestamp.
- Rearranged the order of components in pak_depak.bd for clarity and consistency.
- Adjusted BRAM writer logic in bram_writer.vhd for improved data handling and comments for clarity.
- Enhanced depacketizer.vhd with additional comments and logic adjustments for better data reception.
- Refined divider_by_3.vhd to optimize division calculations and improve clarity in comments.
- Improved img_conv.vhd with better state management and comments for the convolution process.
- Updated led_blinker.vhd to enhance readability and maintainability with clearer comments.
- Enhanced packetizer.vhd to improve data handling and added comments for better understanding.
- Adjusted rgb2gray.vhd to include standard library comments for consistency.
- Updated test.py to improve image processing logic and added visualization for differences.
- Added new binary files for test_nopath.exe and archived project files for lab2 and pak_depak.
- Updated Vivado project files to ensure correct paths and settings for synthesis and implementation.
2025-04-25 00:43:10 +02:00
5cabb20fdd Refactor packetizer and depacketizer components; update test scripts and images
- Modified the graph structure in pak_depak.bda to correct node and edge connections.
- Adjusted testbench for packetizer (tb_packetizer.vhd) to fix data values and packet sizes.
- Enhanced packetizer.vhd to manage footer sending based on last signal.
- Removed obsolete executable file LAB2-Test_new.exe.
- Updated Python test script (test.py) to include new test case for depack > pack functionality and improved image handling.
- Altered Vivado project files to reflect changes in simulation and synthesis settings.
- Deleted unnecessary test executable and added new image for depack > pack testing.
2025-04-24 17:23:56 +02:00
5995a532f5 Refactor testbench for bram_writer: update description, increase image size, and enhance signal handling for improved simulation accuracy 2025-04-23 01:49:46 +02:00
722b479811 Create design folder and update projects 2025-04-22 22:56:28 +02:00
f014f8c341 Refactor and clean up project files
- Removed obsolete GraphML file `pak_depak.bda` and UI file `bd_c9b29a54.ui`.
- Updated `rgb2gray.vhd` to improve signal handling and state machine logic.
- Created new Vivado project files for `depacketizer_test`, including testbench configuration.
- Adjusted `pak_depak.xpr` to disable the FIFO module and set the top module correctly.
- Updated `rgb2grey_test.xpr` to modify simulation launch settings.
2025-04-22 22:32:01 +02:00
e2bcbf7d31 Add testbench for packetizer: implement behavioral testbench, configure simulation settings, and define stimulus for packetization process 2025-04-22 16:24:22 +02:00
47fca59a97 Refactor img_conv and tb_img_conv: enhance state management, improve signal handling, and add varied memory initialization for convolution processing 2025-04-20 00:37:40 +02:00
a054085341 Add testbench for LED blinker, enhance bram_writer with state management, and update test script for overflow/underflow handling 2025-04-17 22:55:49 +02:00
667632bfa3 Enhance bram_writer and testbench: add data handling for convolution, update state machine, and introduce new configuration files for simulation 2025-04-17 21:29:02 +02:00
4433b3f457 Add pak_depak design files and update project references
- Created new design file `pak_depak.bd` with components including `proc_sys_reset`, `clk_wiz`, `AXI4Stream_UART`, `depacketizer`, and `packetizer`.
- Added associated architecture file `pak_depak.bda` for design representation.
- Introduced UI configuration file `bd_c9b29a54.ui` for graphical representation of the design.
- Updated project file `lab2.xpr` to replace references to old source files with new ones.
- Added new project file `pak_depak.xpr` for the pak_depak design with necessary configurations and file sets.
2025-04-15 17:27:38 +02:00
b2d3060247 Refactor image processing components: update bit depth in rgb2gray and divider_by_3, enhance img_conv architecture, and adjust simulation settings 2025-04-11 18:06:02 +02:00
c712b160cc Refactor RGB to Grayscale conversion: update divider component and add testbench 2025-04-11 13:00:46 +02:00
0d805b93b6 Refactor RGB to Grayscale Converter and Add Divider Component
- Updated the rgb2gray.vhd file to improve readability and structure, including consistent casing for keywords and signals.
- Implemented a new divider_by_3 component to calculate the grayscale value by dividing the sum of RGB channels by 3.
- Enhanced the state machine in rgb2gray to handle RGB input and output grayscale values correctly.
- Updated the Vivado project file to include the new divider_by_3.vhd for synthesis and simulation.
- Modified vhdl_ls.toml to include unisim files for third-party library support.
2025-04-11 01:50:19 +02:00
1e84f090b7 Implement state machine in depacketizer for packet processing and add top auto-set option in project configuration 2025-04-09 12:52:28 +02:00
360ae72198 Reorder reset, sys_clock and USB UART ports in lab_2_wrapper and update synthesis flow mode in lab_2.bd 2025-04-09 11:40:21 +02:00
cd5d1b8a0c Add new AXI4-Stream UART IP and update .gitignore for Lab2 files 2025-03-31 18:35:29 +02:00