- Updated .gitignore to exclude virtual environment and additional test files.
- Modified diligent_jstk.bd to reorganize interface nets for clarity.
- Adjusted diligent_jstk.bda to correct node attributes and edges.
- Revised diligent_jstk_wrapper.vhd to ensure proper port declarations.
- Enhanced uart_viewer.py for improved image handling and serial connection checks.
- Updated diligent_jstk.xpr and lab3.xpr for correct file paths and run configurations.
- Added requirements.txt to specify project dependencies for Python packages.
- Updated lab_3.bda to correct node connections and attributes.
- Enhanced LFO.vhd with improved signal handling and clamping logic.
- Modified all_pass_filter.vhd to ensure proper data transfer.
- Adjusted balance_controller.vhd to incorporate reset logic in signal assignments.
- Cleaned up effect_selector.vhd by removing unnecessary assignments.
- Improved led_level_controller.vhd for better readability and functionality.
- Refined moving_average_filter_en.vhd to streamline AXIS assignments.
- Enhanced mute_controller.vhd for clearer data flow management.
- Updated lab3.xpr to correct file paths and simulation settings.
- Created `tb_volume_multiplier_behav.wcfg` for waveform configuration of the volume multiplier testbench.
- Added `volume_multiplier.xpr` project file for the volume multiplier design.
- Created `volume_saturator.xpr` project file for the volume saturator design.
- Added `volume_saturator_tb_behav.wcfg` for waveform configuration of the volume saturator testbench.
- Updated the date in the diligent_jstk_wrapper.vhd file.
- Modified the testbench (tb_digilent_jstk2.vhd) to ensure proper data transmission and added a delay to simulate real response time.
- Adjusted the digilent_jstk2.vhd file to refine the state machine logic for sending and receiving data, including a new IDLE state and improved handling of the SPI communication.
- Enhanced uart_viewer.py to automatically detect the Basys3 board's serial port, improving user experience and reducing configuration errors.
- Updated the Vivado project file (diligent_jstk.xpr) to reflect changes in simulation and synthesis settings, ensuring compatibility with the latest design updates.
- Created board.xit for physical constraints related to UART interface.
- Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata.
- Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl.
- Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings.
- Configured file sets and simulation options for both projects.
- Created a new Block Design Archive (lab_3.bda) for LAB3, defining nodes and edges for the design.
- Added a placeholder README file in the simulation directory.
- Initialized a Vivado project file (lab3.xpr) with configuration settings and source files for synthesis and simulation.
- Updated vhdl_ls.toml to include LAB3 source and simulation files for VHDL language server support.
- Created LFO entity for low-frequency oscillation control.
- Added all_pass_filter entity for signal processing.
- Implemented balance_controller for audio balance adjustments.
- Developed debouncer to stabilize input signals.
- Introduced digilent_jstk2 for joystick data handling.
- Added edge_detector_toggle for edge detection functionality.
- Created effect_selector to manage audio effects based on joystick input.
- Implemented jstk_uart_bridge for communication between joystick and UART.
- Developed led_controller for LED management.
- Introduced led_level_controller for controlling multiple LEDs.
- Created moving_average_filter for smoothing input signals.
- Added moving_average_filter_en with enable functionality.
- Implemented mute_controller to handle mute functionality.
- Developed volume_controller for volume adjustments.
- Introduced volume_multiplier for scaling audio signals.
- Created volume_saturator to ensure audio signals stay within bounds.
