722b479811
Create design folder and update projects
2025-04-22 22:56:28 +02:00
f014f8c341
Refactor and clean up project files
...
- Removed obsolete GraphML file `pak_depak.bda` and UI file `bd_c9b29a54.ui`.
- Updated `rgb2gray.vhd` to improve signal handling and state machine logic.
- Created new Vivado project files for `depacketizer_test`, including testbench configuration.
- Adjusted `pak_depak.xpr` to disable the FIFO module and set the top module correctly.
- Updated `rgb2grey_test.xpr` to modify simulation launch settings.
2025-04-22 22:32:01 +02:00
e2bcbf7d31
Add testbench for packetizer: implement behavioral testbench, configure simulation settings, and define stimulus for packetization process
2025-04-22 16:24:22 +02:00
47fca59a97
Refactor img_conv and tb_img_conv: enhance state management, improve signal handling, and add varied memory initialization for convolution processing
2025-04-20 00:37:40 +02:00
a054085341
Add testbench for LED blinker, enhance bram_writer with state management, and update test script for overflow/underflow handling
2025-04-17 22:55:49 +02:00
667632bfa3
Enhance bram_writer and testbench: add data handling for convolution, update state machine, and introduce new configuration files for simulation
2025-04-17 21:29:02 +02:00
7ee12b37fe
Enhance bram_writer: add image size parameter, improve state machine for data handling, and refine signal management for better performance
2025-04-17 19:21:15 +02:00
1d226709ac
Refactor bram_writer: streamline entity definition, remove unused signals, and enhance state management for improved clarity and functionality
2025-04-17 17:25:21 +02:00
9bf8c21957
Refactor bram_writer and test script: improve code readability, update package installation method, and enhance image processing logic
2025-04-17 01:24:18 +02:00
f363f09506
Implement finite state machine in bram_writer for improved data handling and convolution control
2025-04-16 13:02:48 +02:00
4433b3f457
Add pak_depak design files and update project references
...
- Created new design file `pak_depak.bd` with components including `proc_sys_reset`, `clk_wiz`, `AXI4Stream_UART`, `depacketizer`, and `packetizer`.
- Added associated architecture file `pak_depak.bda` for design representation.
- Introduced UI configuration file `bd_c9b29a54.ui` for graphical representation of the design.
- Updated project file `lab2.xpr` to replace references to old source files with new ones.
- Added new project file `pak_depak.xpr` for the pak_depak design with necessary configurations and file sets.
2025-04-15 17:27:38 +02:00
b2d3060247
Refactor image processing components: update bit depth in rgb2gray and divider_by_3, enhance img_conv architecture, and adjust simulation settings
2025-04-11 18:06:02 +02:00
c712b160cc
Refactor RGB to Grayscale conversion: update divider component and add testbench
2025-04-11 13:00:46 +02:00
0d805b93b6
Refactor RGB to Grayscale Converter and Add Divider Component
...
- Updated the rgb2gray.vhd file to improve readability and structure, including consistent casing for keywords and signals.
- Implemented a new divider_by_3 component to calculate the grayscale value by dividing the sum of RGB channels by 3.
- Enhanced the state machine in rgb2gray to handle RGB input and output grayscale values correctly.
- Updated the Vivado project file to include the new divider_by_3.vhd for synthesis and simulation.
- Modified vhdl_ls.toml to include unisim files for third-party library support.
2025-04-11 01:50:19 +02:00
0912887822
TEMP Implement state machine in packetizer for improved packet handling
2025-04-09 12:59:00 +02:00
1e84f090b7
Implement state machine in depacketizer for packet processing and add top auto-set option in project configuration
2025-04-09 12:52:28 +02:00
360ae72198
Reorder reset, sys_clock and USB UART ports in lab_2_wrapper and update synthesis flow mode in lab_2.bd
2025-04-09 11:40:21 +02:00
cd5d1b8a0c
Add new AXI4-Stream UART IP and update .gitignore for Lab2 files
2025-03-31 18:35:29 +02:00
06afed32a3
Update README.md to include test files and programs section
2025-03-29 00:58:19 +01:00
a5264642a6
Add new VHDL entities for image processing and update test scripts for Lab2
2025-03-29 00:50:32 +01:00
58f8384507
Fix KittCarPWM to adjust BIT_LENGTH by reducing it by one
2025-03-25 10:36:34 +01:00
8826072328
Refactor KittCarPWM to use dynamic bit lengths for PWM and timing counter
2025-03-24 15:55:54 +01:00
5db3a71766
fix typo
2025-03-24 13:30:32 +01:00
0b60a93835
Update README.md
2025-03-24 13:20:28 +01:00
ac8b35ff73
Refactor PulseWidthModulator entity parameters and update README for project setup
2025-03-24 13:16:39 +01:00
68ca4a6ea2
Refactor VHDL testbench and update library paths in vhdl_ls.toml
2025-03-24 00:28:49 +01:00
b8a52e0624
Update README.md
2025-03-24 00:23:07 +01:00
f9661d9630
Update README.md
2025-03-23 23:42:34 +01:00
Davide Cavagnola
71043ea6ec
Update vhdl_ls.toml
2025-03-23 17:05:16 +01:00
Davide Cavagnola
77ad3b2c6c
Update vhdl_ls.toml
2025-03-23 17:04:51 +01:00
89ecaadc73
Setup VHDL LS extension
2025-03-23 12:50:02 +01:00
2dd1de3ac9
add /docs
2025-03-22 19:29:13 +01:00
2370f56d07
Update KittCarPWM to keep the first LED always on
2025-03-22 19:15:43 +01:00
7b51306696
Refactor KittCar and KittCarPWM for improved LED control; update simulation settings and add testbench
2025-03-22 17:02:22 +01:00
f6c568b416
Refactor KittCarPWM logic for improved LED direction handling and clean up Vivado project settings
2025-03-21 17:47:28 +01:00
038ea73291
Add PulseWidthModulator and update KittCarPWM; adjust simulation launch time
2025-03-21 16:20:55 +01:00
35426ab1cf
Fix KittCar.vhd
2025-03-20 22:57:31 +01:00
163ad448f8
Update .gitignore and enhance README.md; add new VHDL files for KittCarPWM, ShiftRegisters, and PulseWidthModulator
2025-03-20 15:05:27 +01:00
c29b83ba63
Enhance README.md with improved structure and clarity
2025-03-19 17:41:06 +01:00
52af51ac18
remove KittCar_v1.1.vhd
2025-03-19 17:22:21 +01:00
b6b6697561
final fix
2025-03-19 17:20:16 +01:00
482b1ea274
add more vesions
2025-03-19 16:30:40 +01:00
Davide Cavagnola
25afc34966
Update README.md
2025-03-18 11:55:21 +01:00
Davide Cavagnola
3e1f49f043
Update README.md
2025-03-18 11:53:08 +01:00
9e8805b4e5
add .xpr
2025-03-18 09:57:38 +01:00
b51f25e81b
final commit
2025-03-18 00:27:28 +01:00
797b2c0be8
cleanup
2025-03-18 00:24:10 +01:00
2a88d406f8
commit
2025-03-18 00:21:11 +01:00
4e1e66a5e4
commit
2025-03-18 00:16:41 +01:00
Davide Cavagnola
0c2be2b94a
Delete LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd
2025-03-18 00:11:15 +01:00
